December 17, 2002 3:39 PM PST
Sun's UltraSparc doubles down for power
Using so-called dual-core processors is an important step in taking advantage of chip manufacturing advances to make server computers more powerful without consuming much more power. IBM already has made the switch to this dual-core technology with its Power4 processor. Sun and Hewlett-Packard are next in line, while Intel's Itanium won't make it to dual-core models until mid-decade.
Sun's dual-core technology will first emerge in the UltraSparc IV processor, Andy Ingram, vice president of marketing at Sun, said in a media briefing.
UltraSparc IV is important not just because it's a new, faster chip, but because Sun's existing servers will accommodate it. That upgrade option can be a draw for customers who buy servers they expect to use for years.
Sun now has prototype UltraSparc IV processors in hand, Ingram said. Texas Instruments builds Sun's high-end processors.
Sun Chief Executive Scott McNealy said in October that servers using UltraSparc IV would begin shipping about a year from then.
Sun also has prototypes of the UltraSparc IIIi processor, code-named Jalapeno, a product with high-speed cache memory integrated into the chip, a company representative said.
HP uses its own PA-RISC processors in its servers and is moving to Intel's Itanium, which HP helped design. PA-RISC will become a dual-core product when HP puts two of its current PA-8700 chips onto the same silicon to become the PA-8800, code-named Mako. The processor is expected to run at 1GHz speeds, HP has said.
Even though dual-core Itaniums won't arrive for years,
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One reason Itanium will be a relatively late arrival to the dual-core realm is its large size, said Insight 64 analyst Nathan Brookwood. Because there are practical limits to the physical size of a chip, it's harder to squeeze two large processors onto a single piece of silicon. Much of Itanium's surface area is occupied by its cache memory; the next-generation Madison version of Itanium will come with as much as 6MB of cache.