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The project, called the Western Institute of Nanoelectronics (WIN), will have its administrative headquarters at UCLA Henry Samueli School of Engineering and Applied Science, one of the four member institutions. Scientific and technical work will also be dispersed over the campuses of Stanford, the University of California at Berkeley and UC Santa Barbara.
WIN is being established with grants of $18.2 million to be dispersed over four years, largely from semiconductor companies with an interest in breakthroughs in spintronics, which holds promise in minimizing power consumption for next-generation consumer electronics. Chipmaker Intel granted the project $2 million, along with $10 million in equipment. The Nanoelectronics Research Initiative, a grant funded by computer companies IBM, Texas Instruments, Advanced Micro Devices and Intel, among others, provided $2.38 million.
The group expects the participating universities to spend more than $200 million in infrastructure and personnel support for the project over those four years.
Researchers say that chipmakers in the coming years will likely hit a barrier in Moore's Law that could prevent chip designers from gaining performance by shrinking their chips, the engine behind the exponential growth in computer power for more than three decades.
"Simply put, today's devices, which are based on complementary metal oxide semiconductor standards, can't get much smaller and still function properly and effectively. That's where spintronics comes in," said UCLA engineering professor Kang Wang, who will act as director of the institute.
Spintronics uses the spin of an electron to carry digital information. Until now and for years to come, data-processing technology has relied on charge-based devices, ranging from vacuum tubes to million-transistor microchips. Conventional electronic devices move these electric charges around, ignoring the spin that piggybacks on each electron. The study of spintronics intends to use that extra spin, turning those electrons into one smooth reactive chain of motion.
The metaphorical name of the technology derives from way electrons are said to spin.
See more CNET content tagged:
electron, spin, chip company, CMOS, Intel






Startup time is determided by necessity to load OS image and other programs into memory (not by processing power) because memory contents is lost when power is off. Modern computer systems have a number of other bottlenecks that slow them down. E.g. memory access is times slower than processor can operate - we need CPU caches. HDD access is astonishingly slow - we need filesystem caches. Ratio between CPU operation delays and HDD delays is about 1000000 times! This IS the problem that should be solved.
And exciting technology that probably can solve many of these problems (and therefore boost performance, especially if software account on it) is described at this site http://atomchip.com/. And it is already in production according to the site.
Although I have yet to see any performance tests with real-world applications of systems with this memory architecture.
BTW Using single type of memory for all needs could significantly simplify operating system design and applications architecture in general. Just think about the fact that we do not need any persitence frameworkds and complex DBMSes anymore if we do not lose memory contents after power-off.
It seems I went offtopic a little...
know this because I work in this area. You only have to look at
the pictures on this page http://atomchip.com/_wsn/
page3.html to see that. On top of this, quantum computers are
so completely different to the classical model of computation,
that an existing OS would be able to operate.
On the memory side of things, it would be nice to see old HDs
phased out. Unfortunately flash memory cannot be written to
enough times to make this a viable option yet, and I think a
large parallel bank of flash memory would be the best
alternative to date.
- 1.2 Petabyte Spintronics Technology
- by grey_eminence March 10, 2006 6:40 PM PST
- http://colossalstorage.net
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