February 25, 2005 4:00 AM PST
IBM server design drops Itanium support
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separate chip was used for the processor interface, but with X3, IBM integrated that interface into the main part of the chipset. That integration makes the chipset cheaper but also would have made Itanium support more expensive.
The X3 chipset is used in IBM's four-processor x336 server, due to go on sale within 90 days, but X3 also will see use on higher-end multiprocessor systems, Bradicich said.
"We have a lot of flexibility. We built this X3 Hurricane chip to scale for four, eight, 16 or 32 processors, plus it will accommodate dual-core in each of those configurations," he said. IBM spent more than $100 million over three years developing X3, he added.
Hurricane includes two major components, controllers for the computer's memory subsystem and a "scalability port" that is used to link four-processor groups together. With Hurricane's predecessor, the "Cyclone" memory controller and "Twister" scalability port controller were separate chips, Bradicich said.
The memory controller was once linked to a large pool of high-speed external memory called a cache, but X3's access speeds are fast enough that the cache no longer is needed. The technology for addressing the cache memory remains in the chipset, though, as a way to speed access to needed data, he said.
With X3, one component, code-named Calgary, is still separate. It links Hurricane to the input-output subsystem, which lets a computer use the faster PCI-X 2.0 connection technology compared with the PCI-X of the X3's predecessor. A new version of Calgary coming by the end of the year will build support for a newer input-output system called PCI Express.
X3 also continues support for hardware partitioning technology that lets each four-processor unit house a separate operating system, Bradicich said.
The communication channel that links the processor to the chipset is called the front-side bus. X3, like Intel's chipsets, uses a 667MHz front-side bus that's substantially faster than the 400MHz bus on current Xeons geared for four-processor machines. And like Intel's chipset, X3 also employs dual front-side buses for each chip, a move that makes it easier to accommodate the communication demands of future dual-core models, Bradicich said.
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