November 11, 2002 10:55 AM PST

IBM bakes new 3D circuit design

Related Stories

Intel unfurls experimental 3D transistors

September 16, 2002

AMD joins transistor trend

September 10, 2002

Intel shrinks chips to 90 nanometers

March 12, 2002

Start-up has feel for 3D chips

December 5, 2001
IBM says building better microchips is kind of like baking a cake.

Researchers at Big Blue have devised a new 3D circuit design that uses two or more layers of transistors, the basic building blocks of a chip, stacked in the same way a baker would create a multilayered cake.

The 3D design "adds second or multiple...layers on top of what's already there," said Kathryn Guarini, IBM's lead researcher on the project. So "instead of a single layer of transistors, we have two or three or more."

This new circuit design, which is in its early stages at IBM Research, could one day lead to more powerful chips, Guarini said. By layering transistors instead of placing them side by side as is done now, Big Blue can increase the number of transistors in a chip, boosting performance.

IBM could also reduce the length of the metal interconnects used to link the transistors, Guarini said. This would enhance performance in a manner similar to a process shrink, during which chipmakers change their manufacturing processes to produce smaller features inside chips.

A third advantage of the design is a potentially new way of mixing different kinds of circuits inside the same chip, Guarini said. For example, IBM could build new networking chips by adding a layer of circuits to handle optical networking.

Although the new design has great potential, it's still fairly green, according to IBM. The company has yet to take the next step of connecting the various layers of circuit in its labs, and it isn't discussing when or if the technology will make it to production.

The company also has to navigate the potential pitfalls, such as how much power is used up, when adding a larger number of transistors to a chip design.

"Power consumption is a concern," Guarini said. "We may have to be concerned about what we put on the upper layers."

Intel and several others, including Matrix Semiconductor, have also gone public with 3D designs. Intel's experimental Tri-Gate transistor uses a 3D design, stacking its three gates--tiny pathways for electricity--on top of one another. Meanwhile, Matrix has a 3D circuit design for multilayered memory chips, similar in concept to IBM's.

IBM will present a paper on the new circuit design at next month's International Electron Devices Meeting chip design conference in San Francisco.

 

Join the conversation

Add your comment

The posting of advertisements, profanity, or personal attacks is prohibited. Click here to review our Terms of Use.

What's Hot

Discussions

Shared

RSS Feeds

Add headlines from CNET News to your homepage or feedreader.