January 15, 2007 9:00 PM PST
Can HP fool Moore's Law?
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Researchers from HP Labs plan to publish a paper this month that outlines how it may become possible to substantially increase the performance of certain types of chips, and reduce their power consumption, by replacing the communication wires inside chips with an overhead grid of tiny nanowires.
The architectural concept could prove a novel way to help tackle one of the major problems facing semiconductor designers--how to continue to shrink chips and the components inside chips.
As described in Moore's Law, chip manufacturers have been able to simultaneously boost performance and cut the cost of production by reducing the size of transistors and interconnects (the metallic wires that link up transistors) every two years.
Downsizing those parts, however, has become more more difficult and expensive. That in turn has forced designers to make trade-offs between performance, energy efficiency and cost.
But a shift to a crossbar structure would essentially change the shrinkage formula, said Stan Williams, an HP senior fellow and director of the Quantum Science Research group in HP Labs.
By removing the traditional interconnects, the size of a given chip would naturally and drastically shrink. Performance would increase, but the chips could still be made out of traditional transistors. Cost, would ideally decline because the advance wouldn't require investing billions of dollars in new semiconductor manufacturing equipment. Power consumption would likely fall, at the same time.
"People have been wringing their hands about the end of Moore's Law, but so much of the discussion has been around, 'Oh, gee, it's so hard to shrink transistors any more,'" Williams said in an interview. "The issue here is we have--at least for one type of chip--proof in principle that it is possible to increase chip density, decrease power consumption, and increase operating speed without shrinking a transistor."
At the crossbar
The crossbar is one of the more prominent ideas to emerge from HP Labs in the past several years. The company has demonstrated how the structure can be used to improve memory chips, compensate for manufacturing defects and help circuits do calculations.
Although HP has largely exited the chip business, it has put more emphasis on gaining revenue from licensing technology. If the crossbar concept were to take off, HP could gain millions of dollars in royalties.
So far, the company has created a simulation of a field-programmable gate array (FPGA) with a crossbar grid, and it hopes to have a prototype by the end of the year, Williams said. By 2010, manufacturers may be able to incorporate the crossbar communications system into commercial chips.
Eventually, it's possible that the concept could be incorporated into other types of chips. Many analysts already predict that the copper interconnects that supplanted aluminum in the 1990s will themselves have to get replaced.
Williams and HP's Greg Snider are studying the concept with an FPGA, which is a chip that can be programmed for many different functions, in part because that's where the greatest gains could be found. In an FPGA, different functional blocks are wired directly to each other through interconnects, sort of like an old-fashioned intercom system.
As a result, any increase in the functional blocks in an FPGA leads to a geometric increase in the number of data pathways.
"In an FPGA, all of the communications stuff can take up 80 percent of the chip area," Williams said.
The crossbar system would eliminate the static plumbing in traditional chips with an intelligent communications system that would only connect functional blocks when they needed to be connected. (Some of the HP Labs work relies on earlier research from Stony Brook University in New York.)
The potential benefits could be numerous. With a dynamic communications network, certain functional blocks or transistor areas could be put to sleep when not in use, thereby cutting power. Manufacturers could also salvage troubled multicore chips by circumventing flawed circuitry.
"You don't have to consign it to the junk heap because of one bad transistor," Williams said.
HP estimated that an FPGA made with 45-nanometer transistors and a grid of nanowires measuring 4.5 nanometers across would be only 4 percent as large as a standard FPGA made on the 45-nanometer process. (Chips built on that 45-nanometer process are expected to come out at the end of this year. The nanometer measurement refers to the average feature size on a chip. A nanometer is a billionth of a meter.) The clock speed on the hypothetical chip would be slower, but the amount of energy consumed per calculation would be lower.
The crossbar structure itself could be made out of aluminum or copper nanowires that are smaller than today's interconnects. The shrinkage problem would also be addressed with the adoption of a new process called imprint lithography.
In traditional lithography, a light beam is used to "draw" a trench in silicon. The trench then gets dug out through chemical processes and filled with aluminum. Imprint lithography looks like it sounds: a mold is pressed into treated silicon, and the resulting imprint is then filled with metal.
The imprint creates smaller lines than traditional lithography, but it hasn't yet been adopted on a mass scale. The technique works best when the circuit lines are fairly regular, and that ties in with HP's crossbar work: the crossbar grid consists of two layers of parallel wires at 90 degree angles.
Hard-drive makers are thinking of adopting the imprint technique for creating patterns in future hard-drive media.
The paper will come out in the January 24 edition of Nanotechnology, and HP is hoping to make a splash.
"We think that is a fairly big deal," Williams said.
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