December 1, 2003 4:00 AM PST
Intel scientists find wall for Moore's Law
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Granted, that end likely won't come for about two decades, but Intel researchers have recently published a paper theorizing that chipmakers will hit a wall when it comes to shrinking the size of transistors, one of the chief methods for making chips that are smaller, more powerful and cheaper than their predecessors.
Manufacturers will be able to produce chips on the 16-nanometer manufacturing process, expected by conservative estimates to arrive in 2018, and maybe one or two manufacturing processes after that, but that's it.
Semiconductor makers won't be able to shrink transistors much, if at all, beyond 2021, according to a new paper from Intel.
Transistor shrinkage is one of the main drivers of Moore's Law, so chipmakers are going to have to start looking for new ways to make their chips more powerful--and less expensive. Otherwise, the pace of progress in the IT industry could begin to slow.
Although it's not unusual for researchers to theorize about the end of transistor scaling, it's an unusual statement for researchers from Intel, and it underscores the difficulties chip designers currently face. The size, energy consumption and performance requirements of today's computers are forcing semiconductor makers to completely rethink how they design their products and are prompting many to pool design with research and development.
Resolving these issues is a major goal for the entire industry. Under Moore's Law, chipmakers can double the number of transistors on a given chip every two years, an exponential growth pattern that has allowed computers to get both cheaper and more powerful at the same time.
Mostly, the trick has been accomplished through shrinking transistors. With shrinkage tapped out, manufacturers will have to find other methods to keep the cycle going.
These issues will likely be widely discussed this week, when the International Technology Roadmap for Semiconductors is unveiled in Taiwan. The ITRS, which is comprised of several organizations, including the Semiconductor Industry Association, outlines the challenges and rough timetable for the industry for 15 years. A new version of the plan will be released in Taiwan on Dec. 2.
Still, Gargini said, researchers are exploring a variety of ideas, such as more efficient use of electrons or simply making bigger chips, to surpass any looming barriers. Other researchers likely will dispute these conclusions.
"We cannot let physics beat us," he said, laughing.
The distinguished circuit
The problem chipmakers face comes down to distinction and control. Transistors are essentially microscopic on/off switches that consist of a source (where electrons come from), a drain (where they go) and a gate that controls the flow of electrons through a channel that connects the source and the drain.
When current flows from the source to the drain, a computer reads this as a "1." When current is not flowing, the transistor is read as a "0." Millions of these actions together produce the data inside PCs. Strict control of the gate and channel region, therefore, are necessary to produce reliable results.
Gargini likens the phenomenon to a waterfall in the middle of a trail. If a person can't see through it, they will take a detour around it. If it is only a thin veil of mist, people will push through.
"Where you have a barrier, the electrons penetrate a certain distance," he said. "Once the two regions are close enough, because of tunneling, the charge will go from A to B, even when a voltage is not applied to the gate."
At this point, a transistor becomes unreliable as a source of basic data, because the probability of spontaneous transmission is about 50 percent. In other words, Heisenberg's uncertainty principle is in action, because the location of the electrons can't be accurately predicted.
In chips made on a 16-nanometer technology process, the transistor gate will be about 5 nanometers long.
"At 5-nanometer gate dimension, I would have to agree with them," said Craig Sander, vice president of process technology development for AMD. "I think we will find applications that don't require that we stay on such an aggressive roadmap."
When these chips will start to be produced is a matter of debate. On paper, new manufacturing processes come out every two years. Chips made on the 90-nanometer process, which contain gate lengths of about 37 nanometers, are just starting to be produced. On a two-year cycle, this would mean that 16-nanometer chips would appear in 2013 with the barriers preventing new, smaller chips in 2015.
Manufacturers, however, have had to delay the introduction of new processes recently. Using a three-year calendar, 5-nanometer chips won't hit until 2018 or 2019, putting a barrier generation at about 2021. The ITRS timetable will provide more details about the different manufacturing technologies for a given year.
The tunneling effects, Gargini said, will occur regardless of the chemistry of the transistor materials. Several researchers over the years have predicted the end of Moore's Law but made the mistake of extrapolating on the basis of existing materials.
Designers, however, continually change the materials and structures inside semiconductors. Intel and rival Advanced Micro Devices, for instance, are looking at replacing silicon transistor gates with metallic gates so that chips can be mass-produced with 45-nanometer manufacturing--expected between 2007 and 2009. Gates on this process will be about 18 nanometers, according to the ITRS timetable.
The concept behind the Intel researchers' paper was, "why don't we do something based entirely on fundamental principles?" Gargini said. "The beauty of our paper is that it is independent of materials."
Theoretically, chip designers could squeeze the size a bit more. "You could probably go to 4" nanometers, he said, but that would require increasing the energy needed to run the chip to make the barrier less susceptible to tunneling.
Energy a burning problem
Energy consumption, however, is already a major problem for chip designers. Not only is it increasingly difficult to provide energy to a chip, the ambient power-driven heat can cause major malfunctions.
"Scaling for binary switches, packed to maximum density, is ultimately limited by the system capability to remove heat," the paper stated. "Simultaneous gains in packing density and speed of operation will eventually be replaced by a trade-off between packing density and speed in order to satisfy heat removal constraints."
Like other researchers, Gargini sees no easy solution to energy consumption. Active cooling systems can reduce the internal temperature of computers but require independent energy sources, which create about as much heat as they remove. As a result, even if transistors with gate lengths that measure 3 nanometers could be made, a chip that contained them would hypothetically overheat itself.
"From a total energy point of view, you are not fooling mother nature," Gargini said.
Even if the energy consumption and tunneling problems can be solved, transistors will hit a limit when the gate reaches 1.5 nanometers in length, he said. The number comes from a calculation researchers made when examining what is the smallest well from which an electron could be extracted, Gargini said.
Unlike a conventional transistor, where the source, channel and drain sit in a horizontal line, a transistor at the 1.5-nanometer level might be vertically structured. On the shrinkage rules, transistors with this sort of gate would occur about four to six years after the transistors with 5-nanometer gates, or 2017 to 2025.
The soaring costs of making chips
are recasting the industry.
Carbon nanotubes and silicon nanowires are another alternative. Transistors made of these materials are of comparable sizes. Carbon nanotubes have a diameter of 1 to 2 nanometers, but they are stretched lengthwise between a source and drain in experimental transistors. In the end, performance could go up--and energy consumption could decline--but size will stay about the same.
"Exotic structures, such as carbon nanotubes, may find their way into CMOS (Complementary Metal Oxide Semiconductor) applications, not so much driven by acceleration of the scaling cadence, but more likely to enhance the performance of CMOS devices, or perhaps to simplify fabrication," the paper stated. "Even if entirely different electron transport devices are invented for digital logic, their scaling for density and performance may not go much beyond the ultimate limits obtainable with CMOS technology, due primarily to limits on heat removal capacity."
Another alternative is to make the chips bigger, add transistors by adding more real estate or building 3D chips, in which layers of transistors form a high rise. These solutions have been conjectured by Intel co-founder Gordon Moore and Stanford professor Tom Lee, among others.
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