Intel and ST Microelectronics have come up with a way to put multiple bits of data in a single memory cell in phase change memory, a breakthrough that effectively doubles the technology's density.
Now if they could only get the stuff to market.
Phase change memory is a type of memory made out of materials similar to those used to make CDs and DVDs. A tiny laser rapidly heats up a small bit, and in the process transforms the structure of the bit from crystalline to amorphous. Reversing the process can change the bit from having an amorphous character to a crystalline one again.
A light beam reflects off the bit, and its state (amorphous or crystalline) then gets registered as a 1 or 0, the building blocks of data.
The companies have come up with an algorithm that can assign values to two additional intermediate states. To use an analogy, traditional phase change memory can discriminate between water and ice. Now it can recognize vapor, water, sort of solidified water, and solid ice. The companies are presenting a paper at the International Solid State Circuits Conference on a 256-megabit phase change chip that holds multiple data bits per cell.
The companies have formed a joint venture called Numonyx that is supposed to come out with new types of memories. Numonyx looks suspiciously like Ovonyx, the company that pioneered phase change and licenses technology to Intel and ST. (None of these, however, should be confused with Wyld Stallionz, the band from Bill and Ted's Excellent Adventure.)
Industry sources expected Numonyx to make an announcement last year. It didn't. Intel has talked up phase change as a flash replacement for years, but has yet to release chips. (Gordon Moore even mentioned it back in 1970.) Other companies--Philips, Samsung, you name it--are in the same boat. They have prototypes and plans, but no products yet.
But maybe someday.
Someday soon, you might be able to figure out where you are in the world by staring.
Researchers from South Korea's Yonsei University will present a paper at the International Solid State Circuits Conference next week on a system that spits out two-dimensional coordinates for the object or place that a person is focusing on. The same group has worked on several eye interfaces in the past, mostly for people with disabilities. By integrating eye interfaces with GPS information, users can apparently get geographic information. The group presents its paper on Monday, February 3.
ISSCC is one of the premier events in the chip design world. Every year, large companies and universities gather to show off products or concepts that will come to the market in the next few months or years. ISSCC firsts include the first papers on Cell processors (2005); digital signal processors or DSPs (Bell Labs, 1980); RISC chips (UC Berkeley, Stanford, 1984); 100MHz processors (Intel, 1991); and 1GHz processors (Digital; Intel, 2000).
Although sponsored by the University of Pennsylvania, the conference takes place in San Francisco. (The computer business was centered in Philadelphia when ISSCC got started.) Other conference highlights for next week include:
IBM will discuss a version of the Cell processor made on the 45-nanometer process that consumes 40 percent less power and 36 percent less space than current versions. IBM, along with Toshiba and Sony, is trying to percolate the Cell into the market. Right now, the vast majority of Cell chips are used in the PlayStation 3.
Jeff Hawkins, of Palm fame, will show up Monday morning to talk about Hierarchical Temporal Memory, or storing memories in computers the way brains do. His start-up, Numenta, focuses on this.
Intel will describe a low-power chip that uses an in-order execution pipeline, a design concept that Intel hasn't used in its mainstream chips for years. It will also show off an Itanium with 2 billion--count 'em, 2 billion--transistors.
NTT, the Japanese telecom giant, will show off a fingerprint reader that can differentiate between a real and a fake finger.
Future Waves from the U.K. will describe a wireless body network for monitoring vital signs. It's a disposable system for the last meter problem in body sensor networks, the company says. Right afterward, Massachusetts General Hospital will describe a portable MRI machine. (Other health sessions include updates on brain implant research from Brown University and an artificial pancreas from Medtronic.)
Infineon has a paper titled "UMB Fast Hopping Frequency Generation Based on Sub Harmonic Injection Locking" that will come out during the "UWB Potpourri" session on Monday, while the University of Freiberg will present a paper on "A Continuous Time Hexagonal Field Programmable Analog Array."
Just in case you were wondering.
It appears that Intel has turned the clock back several years in terms of chip architecture to reduce power in the upcoming Silverthorne mobile chip.
At the International Solid States Circuits Conference next week, chip designers from the company will discuss a mobile processor based around the x86 Intel Architecture that uses an "in-order pipeline" among other features.
To most people, "in-order pipeline" doesn't mean doodly-squat, but in chip design it's a big deal. Chips with this sort of pipeline, sort of a microprocessor's assembly line, have to perform tasks in a specified manner. If it needs data to perform a specific calculation, everything stops until the data comes in.
Chips with an out-of-order pipeline can perform tasks further down the line. Out-of-order chips have higher performance, but they burn more energy. Intel PC chips have been based around out-of-order pipelines since the mid-'90s. The Pentium Pro was one of the first big hits the company had with this sort of architecture.
Tiny Via Technologies used an in-order pipeline on its low-power C7 chip and will later this year come out with its first out-of-order chip. Glenn Henry, who runs Centaur (Via's chip design group) was the one to tip us off that Silverthorne would be an in-order chip.
Intel did not use the name "Silverthorne" in the conference materials, but the technical details of the chip that the company will discuss at ISSCC, and the details the company has provided about Silverthorne, are the same. Both are described as having 47 million transistors and being made on the 45-nanometer process. The power consumption in the conference entry says the chip will consume less than 2 watts. Silverthorne is said to consume 10 times less than current mobile chips, which puts it in the same range. Companies also don't put far-out prototypes at ISSCC. Usually, they discuss chips about to come out. Silverthorne is due soon.
And both come out of Texas.
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