Nanotech - The Circuits Blog

Intel's Pat Gelsinger

(Credit: Intel)

Editors' note, Monday 6:16 a.m. PDT: Intel and EMC have officially announced executive changes as outlined below. See the new story for more details.

Intel is expected to announce a management shakeup Monday that will see Senior Vice President Pat Gelsinger leaving after 30 years at the chip giant, according to a report in the New York Times.

Management changes will include sales and marketing chief Sean Maloney taking over the company's major chip businesses, while laptop chips head Dadi Perlmutter will take over engineering for all chip divisions, according to the report.

The official announcement is expected before the market opens Monday, according to one person familiar with the changes.

Gelsinger, senior vice president and co-general manager of Intel's Digital Enterprise Group, joined Intel in 1979. He led Intel Labs, which encompasses many Intel research activities, and was Intel's chief technology officer.

Gelsinger has been a high-profile presence at many Intel forums over the years including its marquee Intel Developer Forum event.

Maloney, Intel's sales chief, is also considered to be a possible successor to Intel CEO Paul Otellini.

Intel representatives declined to comment on the report.

Update, Monday 5:36 a.m. PDT: The Wall Street Journal reported overnight that EMC is expected to announce Monday that it is hiring Gelsinger to run its storage products business, along with some software units.

Intel is celebrating its four-decade-long relationship with Stanford University by spotlighting the school's nexus with its top executives.

The Intel-Stanford tie famously began back in 1969 when Stanford electrical engineering alumnus Ted Hoff became Intel employee No. 12. Within two years, he had invented, along with Federico Faggin and Stan Mazor, Intel's flagship product: the microprocessor.

For more than four decades, the Stanford-Intel relationship has been behind the launch of some of Intel's flagship technologies and hundreds of the company's engineering careers. (Almost 1,000 Stanford alumni have worked at Intel and a Stanford University Web page marks this relationship.)

(Credit: Stanford University)

The retirement this month of Intel chairman and former CEO (1998-2005) Craig Barrett, highlights one of the most enduring ties. Barrett was a professor from 1965 until he joined Intel in 1974.

"Industry does a good job at the D part of R&D--but we rely on the tier-one research universities like Stanford on the R side," Barrett said in an interview published on Stanford University's Web site. Barrett cited marquee research at Stanford such as semiconductor device modeling and new packaging technologies.

Senior VP Pat Gelsinger is another Stanford graduate. "We've had great results from the collaboration," said Gelsinger--also quoted in the interview--who earned an masters of science degree in electrical engineering at Stanford in 1985. "In almost every area that Intel is doing work we can point to significant collaboration and research projects with Stanford."

SAN FRANCISCO--Intel plans to bring its first dual-core Atom to market next month, it was revealed here Monday during the Intel Developer Forum. The chipmaker also disclosed more details of the Nehalem processor.

The power-efficient processor will be targeted at Atom-based desktops called nettops. Currently, Intel offers the Atom N230 processor for nettops. This chip has a slightly higher power envelope than the Atom processors built exclusively for mobile devices.

That news was revealed to this reporter by an Intel employee as senior vice president Pat Gelsinger was delivering his IDF keynote, which included more specifics about Nehalem, the family of chips the company plans to begin rolling out in the fourth quarter. Gelsinger, the general manager of Intel's Digital Enterprise Group, showed the first wafer holding individual eight-core processors, detailed the power-saving features of the Nehalem processors, and confirmed future mobile Nehalem processors.

Intel Nehalem processor lineup as shown at IDF 2008

(Credit: Intel)

Also due in September is the six-core Dunnington server processor, the final member of Intel's 45-nanometer "Penryn" family, which will ship to customers next month, Gelsinger said.

Most of his keynote centered on Nehalem, and one of the features Intel was pushing hard at IDF was a technology called Turbo mode.

Turbo mode is essentially a switch that turns off unused processor cores and then uses the remaining active cores more efficiently. This kind of sophisticated power-management technology will be used in both Nehalem-based laptops and servers, according to Gelsinger, and will become increasingly necessary as Intel brings out chips with more cores like the eight-core Nehalem processor due next year.

In short, in multi-core processors, cores not doing much can still use power. So, it's better to use, for example, a couple of cores more efficiently than four cores inefficiently.

The power saving technology is enabled by "an integrated microcontroller which only works on power management," said Rajesh Kumar, an Intel Fellow, who spoke during Gelsinger's keynote. There are about 1 million transistors dedicated solely to power management, Kumar said.

The feature "requires no operating system intervention. It is fully detected and managed by the hardware. If it has detected an idle core, it is able to reallocate that power budget to the other cores," Gelsinger said in an interview after his keynote.

On another front, Intel showed the first eight-core Nehalem chip. "This is the first showing of the eight-core Nehalem-EX," Gelsinger said in his keynote. He said the chip is a monolithic design, meaning that all eight cores are on one piece of silicon.

Nehalem-EP, or Nehalem Efficient Performance, will be a quad-core chip for mainstream servers and workstations. What Intel traditionally calls two-socket servers, Gelsinger said.

The mainstream desktop will be the Core i7. "With the i7 we have high-end desktop and extreme," Gelsinger said. The extreme edition is for overclockers, he said. Enthusiast gamers often overclock processors (ratcheting up clock speed beyond the rated speed) to gain extra performance.

"Turbo Mode" is a linchpin Nehalem technology

(Credit: Intel)

But there will be more pedestrian dual-core versions of Nehalem too. "There will be versions for the desktop that will be dual-core as well," Gelsinger said.

Gelsinger also talked about Intel's plans to put graphics directly onto the same piece of silicon as the processor. This will be a first for Intel.

He described why Intel is putting graphics right next to the processor. "There's a big sucking sound near the CPU. It keeps pulling things closer to it. This is uniquely enabled by Moore's Law...and as things get closer together I'm able to drive down thermal envelopes (i.e., heat) and decrease physical form factors (i.e., enable smaller computer designs)," Gelsinger said.

Gelsinger broke down the future processor lineup--with graphics on the processor die and without--as follows. "Lynnfield and Clarksfield are the versions without graphics. Havendale and Auburndale are the versions with integrated graphics." (Even Intel executives occasionally get confused by all the code names and it took two tries for Gelsinger to get this right.)

During a February earnings conference call, Jen-Hsun Huang, president and CEO of Nvidia, repeated one thing over and over: graphics are in and the central processor is out. There is some truth to this. And Intel's plans for future silicon technology address this head on.

Pat Gelsinger, general manager of the digital enterprise group at Intel, spelled out Intel's strategies for future graphics technology on Monday. He addressed the higher-octane technology that will be built into future "Nehalem" processors and the highly sophisticated "Larrabee" chips that will be offered as "discrete" or standalone products.

First, some perspective. Intel--not Nvidia or ATI--is the world's largest supplier of graphics chips for PCs. The reason is simple. Intel-integrated graphics silicon is shipped in tens of millions of PCs every year. It's a low-cost--and relatively low-performance--solution that many PC vendors opt for. But that doesn't mean Intel is the premier supplier of sophisticated mainstream PC graphics technology. That distinction goes to Nvidia and ATI. Intel is a non-player. This is evidenced by the proliferation of Nvidia- and ATI-based graphics board reviews at enthusiast Web sites and the bigger role that graphics processors from these two companies play in handling increasingly complex visual applications.

And, as the Nvidia CEO has intimated, unless Intel responds aggressively, this could make Nvidia a direct Intel competitor in the future. Nvidia's newest GeForce 9600 GT GPU rivals, at the very least, Intel chips in complexity. It has 64 stream processors--each individually clocked at 1625MHz--and a 256-bit memory interface running at 900MHz and contains more than 500 million transistors.

NvidiaGeForce 9600 GT boards: each Nvidia chip has over 500 million transistors.

(Credit: Nvidia)

To address this, Intel intends to boost integrated graphics performance in Nehalem processors and, for the first time, offer a discrete (standalone) graphics product for high-end markets. Both Nehalem and Larrabee are targeted at the 2009-2010 time frame.

So, how will Intel improve Nehalem integrated graphics? Not surprisingly, more transistors and more bandwidth, according to Gelsinger. "Largely, integrated graphics is as much die area as you can throw at it and as much memory bandwidth as you can give it," Gelsinger said. "So, could we equal discrete graphics performance with integrated graphics? Of course." Gelsinger went on to say that Intel will focus on "more transistor budget, leading-edge process technology, and more memory bandwidth dedicated to integrated graphics."

Logistically, this will be accomplished by turning today's three-chip CPU into a two-chip CPU, he said. That means moving the graphics silicon onto the same die with the main processor. More specifically, the part of the chipset referred to as the "north bridge" is going away. The north bridge contains the memory controller and graphics controller. Both of these components will be moved onto the CPU die. The other part of the chipset referred to as the "south bridge" will remain separate. This includes I/O related components.

But Gelsinger said there are definite limits to what can be done with integrated graphics because of the big power and transistor requirements for high-end discrete (standalone) graphics products. They have "a very different price point and die envelope and power envelope. Some of the (discrete) graphics chips alone are 150 watts. We build whole platforms for less (power) than that," he said.

This is where Larrabee comes in. Gelsinger said that Larrabee--a "many core" chip--will target Nvidia and AMD/ATI's discrete graphics. "Obviously, if we're going to be competing in the discrete graphics marketplace, we think we're going to have to compete well...in terms of traditional benchmarks like 3D Mark," he said, adding that Intel will support traditional graphics interfaces such as DirectX and OpenGL. A big potential plus: since Larrabee cores will be based on the Intel Architecture, developers who already write code for standard Intel microprocessors can develop for Larrabee without learning a completely new architecture.