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May 26, 2009 1:15 PM PDT

Intel, IBM discuss 8-core 'Nehalem' server chip

by Brooke Crothers
  • 10 comments

Intel on Tuesday said it will ship a server chip that contains up to eight processing cores later this year, while IBM showed off a high-end server in the works that uses eight such chips, yielding 64 cores.

Intel's Nehalem-EX architecture supports up to eight processors and each processor can integrate up to eight cores.

Intel's Nehalem-EX architecture supports up to eight processors and each processor can integrate up to eight cores.

(Credit: Intel)

Intel's Nehalem-EX processor, in production later this year and expected to be shipping in high-end server systems by early 2010, will feature up to eight cores inside a single chip that supports 16 threads, according to Boyd Davis, Intel's general manager of the Server Platforms Marketing Group, speaking at a teleconference on Tuesday.

Using threads, Intel essentially doubles the amount of work that can be done on each processing core.

IBM, which participated in the conference, discussed a server currently under development that uses 64 Nehalem-EX cores (eight processors) and can handle 128 threads, according to Alex Yost, vice president IBM BladeCenter. "We're very excited today to be the first to demonstrate Nehalem-EX," Yost said.

Nehalem-EX will also double the memory capacity with up to 16 memory slots per processor socket, and offer four high-bandwidth "QuickPath" Interconnect links.

Intel also said the currently-shipping Nehalem server chip is making market gains. Intel's currently-available Xeon 5500, the first server processor based on Intel's Nehalem architecture, will be "greater than half of shipments" for Intel's high-volume two-processor (aka, "two-socket") server shipments by August, according to Davis.

"Customer acceptance has been quite strong," Boyd said. "From an introduction at the very end of March to representing the majority of our shipments in the market for two-processor servers by the August time frame," he said.

Intel showed off a prototype server that can accommodate four eight-core Nehalem-EX processors.

Intel showed off a prototype server that can accommodate four eight-core Nehalem-EX processors.

(Credit: Stephen Shankland/CNET)
Intel's prototype Nehalem-EX server accommodates eight of these memory cards. They'll use relatively conventional DDR3 memory rather than the FB-DIMM technology Intel's current Xeon 7300 systems.

Intel's prototype Nehalem-EX server accommodates eight of these memory cards. They'll use relatively conventional DDR3 memory rather than the FB-DIMM technology Intel's current Xeon 7300 systems.

(Credit: Stephen Shankland/CNET)
May 19, 2009 8:15 AM PDT

Intel to detail 8-core server chip

by Brooke Crothers
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Updated at 10:00 a.m. PDT with correction about launch of Nehalem-EX processor.

Intel is expected to announce details of an 8-core processor for the high-end server market next week.

The chip itself will not actually ship in systems until late 2009 or early 2010.

The 8-core "Nehalem-EX" Xeon processor is designed for servers that can use more than two processors (referred to as "sockets" in server argot). Currently, Intel is shipping Nehalem Xeon processors for servers with two sockets.

Nehalem is the same architecture used in Intel's Core i7 desktop processor line.

The Nehalem-EX is expected to become Intel's top-line Xeon processor. Currently, the six-core "Dunnington" processor, based on Intel's older Penryn architecture, is Intel's highest-performance chip for multi-processor servers.

Nehalem-EX packs 2.3 billion transistors and its eight cores are capable of executing 16 threads (or tasks) at the same time. The chip also has "integrated power gates" for lowering power-consumption.

The announcement of details is slated for May 26. Boyd Davis, Intel's general manager of Server Platforms Marketing Group, will host the roll-out event and "discuss how this new server product raises the standard in cost-effective RISC replacement solutions," according to an Intel note about the event.

February 3, 2009 9:30 PM PST

Intel at chip conference: More cores, less power

by Brooke Crothers
  • 6 comments

Intel will have a lot to say at the International Solid-State Circuits Conference, spanning the spectrum of silicon from mobile to server processors. Here are a few of the highlights from abstracts of Intel sessions at the ISSCC, which kicks off Sunday in San Francisco.

Nehalem, currently marketed as the Core i7, will scale down to sub-10-watt chips--that's ultraportable notebook (think MacBook Air) territory:

  • "A family of next-generation IA processors...The family has a coherent point-to-point link and integrates memory controller, power-management microcontroller and power-gate transistors and scales from sub-10 to 130W in mobile, desktop and server applications."

Part of the message will be more brute-force silicon: more processor cores, bigger caches--especially for Intel's high-end Xeon processor line:

  • 8-core Xeon processor (aka Nehalem-EX): "An 8-core 16-thread enterprise Xeon processor has 2.3B transistors in 9M 45nm CMOS...operation up to 6.4GT/s...Core and cache shut-off techniques are used to minimize leakage." (Note: '9M" means nine metal layers; "GT/s" is giga-transfers per second.)
  • 6-core Xeon (aka Dunnington): "A monolithic 6-core Xeon processor has 1.9B transistors in 9M 45nm CMOS with a 9MB L2 and 16MB L3 cache and exceeds 1M transactions/minute TPCC in 8-socket configuration. The FSB (Front-Side Bus) I/O circuits are implemented in the center of the die to reduce I/O latency. A low-leakage process variant with cache-sleep and shut-off modes enables low-power 6-core 65W and 4-core 50W variants."

And let's try not to forget Itanium--Intel's, some would say, ill-fated silicon for very-high-end severs:

  • "The clock system for a 700mm2 65nm quad-core Itanium processor has a cascaded PLL (phase locked loop) architecture and enables dynamic frequency switching."

Intel will also present on graphics-related mobile silicon:

  • "A 4-way SIMD (Single Instruction Multiple Data) accelerator for power-constrained microprocessors fabricated in 1.1V, 45nm CMOS occupies 0.081mm2...Enables mode-dependent power savings while achieving wide operating range (1.3V to 230mV) with 2.3GHz, 161mW operation at 1.1V and peak SIMD energy efficiency of 494GOPS/W at 300mV, 50 (degrees) C."

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About Nanotech - The Circuits Blog

Brooke Crothers has served as an editor at large at CNET News, an editor at Dow Jones' Asian Wall Street Journal Weekly, and a senior editor at InfoWorld. His CNET blog covers chip technology and computer systems, and how they define the computing experience. He also contributes to The New York Times' Bits and Technology sections. He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.

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