Despite being slammed by the financial crisis, Intel is not slowing down. It made this crystal clear in a chip technology briefing on Tuesday, putting rivals on notice that the competition will only get more intense.
The world's largest chipmaker is accelerating introduction of new chips, particularly silicon targeted at laptop computers. Intel is achieving this by moving quickly to processors based on next-generation 32-nanometer manufacturing process technology and investing heavily to keep its most advanced chip factories humming, as CEO Paul Otellini pointed out in a speech in Washington, D.C., earlier today.
In a nutshell, this means Intel may move further ahead of the competition as it uses its deep pockets to advance to the newest generation of processors sooner. It also means a renewed emphasis on packing more features--such as better graphics--into mobile chips, particularly those going into laptops.
Intel is moving graphics into the same package as the processor.
(Credit: Intel)"The trend toward notebooks is one of the most important megatrends," said Stephen Smith, vice president and director of business operations for Intel's Digital Enterprise Group. Smith spoke Tuesday in San Francisco during the chip road map briefing, which was also available via teleconference.
Intel will bring out a 32-nanometer mobile processor code-named Arrandale in the fourth quarter of this year that integrates graphics silicon into the same chip package as the main processor or CPU. This is a first for Intel--which to date had offered graphics in a separate chip package. This 32-nanometer dual-core chip was previously expected to appear in 2010.
Another mobile chip due this year, code-named Clarksfield, will pack four cores. This will use current 45-nanometer technology.
Intel road map
(Credit: Intel)Both chips will be based on Intel's new Nehalem microarchitecture, currently used in Core i7 desktop processors.
Smith also reiterated another important technological thrust at Intel when speaking about these upcoming chips: de-emphasizing raw chip speed--usually stated in megahertz or gigahertz--and focusing on "hyper-threading"--or designing chips to handle more than one task at a time without adding more physical processing cores. A thread constitutes a task.
"Clock speeds will stay about the same (as current chips)," Smith said.
Smith also spoke about Westmere, which is Intel's broader term for the effort to move current Nehalem processors (currently marketed as the Core i7) to 32-nanometer technology.
On the server front, an announcement is "imminent" of its first Nehalem processors for servers code-named Nehalem EP, according to Smith. These quad-core processors are designed for servers that have two "sockets"--providing a total of eight processing cores per server.
Intel has completed the development phase of its next-generation manufacturing process that shrinks chip circuitry to 32 nanometers, the chipmaker said Tuesday night.
Intel 32-nanometer SRAM chip
(Credit: Intel)Intel processors are currently made on a 45nm process. Generally, smaller geometries result in faster and more power-efficient processors.
"The company is on track for production readiness of this future generation (of transistors)...in the fourth quarter of 2009," the chipmaker said in a statement.
Intel said it will provide technical details about the 32nm process technology at the International Electron Devices Meeting (IEDM) next week in San Francisco.
Finishing the development phase for 32nm process technology keeps Intel on track with its "tick-tock" strategy. Tick-tock is intended to introduce either a new processor microarchitecture or cutting-edge manufacturing process about every 12 months.
"Producing 32nm chips next year would mark the fourth consecutive year that Intel has met its goal," the company said.
The 32nm paper and presentation "describe a logic technology that incorporates second-generation high-k + metal gate technology, 193nm immersion lithography for critical patterning layers, and enhanced transistor strain techniques," Intel said.
Other Intel IEDM papers will "describe a low power system on chip version of Intel's 45nm process, transistors based on compound semiconductors, substrate engineering to improve performance of 45nm transistors, integrating chemical mechanical polish for the 45nm node and beyond; and, integrating an array of silicon photonics modulators," according to the company's statement.
Intel will also participate in a short course on 22nm CMOS technology.
IBM has added NEC to its growing list of allied companies doing research on next-generation chip manufacturing technology.
On Thursday, IBM and NEC Electronics signed an agreement for joint development of next-generation semiconductor manufacturing process technology, which includes participation in an IBM-led effort focused on 32-nanometer chips and, later, 22-nanometer chips. Currently, companies like Intel and Advanced Micro Devices are bringing 45-nanometer chips to market.
Generally, as geometries get smaller, chips get faster and more power-efficient.
IBM has accumulated a large, eclectic group of chipmakers at its semiconductor fabrication facility in East Fishkill, N.Y., and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, State University of New York.
The area is becoming a hub for chip research that, in essence, is trying to counter the huge multibillion dollar R&D budget of chip giant Intel. Not coincidentally, this isn't far from Advanced Micro Devices' proposed $3 billion chip facility in Malta, NY. AMD also does joint R&D with IBM.
Other members are Singapore-based Chartered Semiconductor Manufacturing, Freescale (formerly part of Motorola), Infineon Technologies, Samsung, STMicroelectronics, and Toshiba.
NEC currently co-develops 45nm and 32nm CMOS process technology with Toshiba and is now extending that scope of collaboration to include the 32nm and finer nodes with IBM and its alliance partners, the Japanese company said.
Specifically, NEC intends to work with the IBM research alliance to develop a common process platform and strengthen development and design ability for system-on-a-chip (SOC) technology--highly integrated silicon typically used in cell phones and consumer electronics devices.
"The new agreement with IBM means that NEC Electronics will develop a common semiconductor process with industry leaders, allowing us to focus on being first to market in areas of eDRAM products and SOC solutions that provide our customers with the added value, such as high reliability and low power consumption," Toshio Nakajima, president and CEO of NEC Electronics, said in a statement.
eDRAM, or embedded DRAM, is high-speed memory usually integrated onto the same piece of silicon as the main processor. This contrasts with traditional DRAM that is external to the processor. eDRAM can be used, for example, in system-on-a-chip designs.
Earlier this year, IBM and its partners unveiled "high-k/metal gate" on silicon manufactured at IBM's 300-millimeter semiconductor fabrication facility in East Fishkill--a technique that Intel also uses.
By implementing high-k/metal gate technology into its leading edge 32-nm technology, the alliance claims performance improvements in circuits of up to 35 percent over 45nm technology at the same operating voltage. The 32nm power reduction over 45nm can be as much as 30 percent to 50 percent depending on the operating voltage, according to IBM.
IBM's research facility in Albany, N.Y., is working toward the ability to build chip features based on 22-nanometer manufacturing technology--and drawing expertise from a diverse group of engineers and scientists.
East Fishkill IBM chip fab
(Credit: IBM)When future generations of chips reach feature sizes in the realm of a billionth of a meter, IBM says, it will take a global village of chip companies, including Advanced Micro Devices, Samsung, Singapore-based Chartered Semiconductor, and Germany-based Infineon, to carry out development and manufacturing.
Currently, IBM and its partners are in the initial stages of 45-nanometer production. (Intel is already in commercial production of 45-nanometer processors.) This will be followed by the 32-nanometer generation and then the 22-nanometer one. The latter presents special challenges because radically new manufacturing processes may be needed. The 22-nanometer generation of chips are expected reach the market in three to five years.
"We now have the capability to do full manufacture to 22 nanometer and beyond in a research facility," said Bernard Meyerson, an IBM fellow, vice president, and chief technologist in the Systems & Technology Group. This will allow IBM and its partners to build "bleeding edge" chip features very early in the process, Meyerson said.
Cooperation keeps members--like AMD and Chartered--competitive with a chip juggernaut like Intel. "We practice an ecosystem strategy. We behave and act as one team. It's not unusual to have an AMD team member leading one team...and Chartered to be leading another," he said. The basic formula is to bring the best and brightest to the United States and headquarter them at IBM's facilities at Yorktown, Fishkill, and Albany, Meyerson said.
In the more immediate future, IBM is also providing AMD (for a considerable fee, of course) with know-how for AMD's 45-nanometer generation of processors that were showcased at CeBit. These processors are due out in the second half of this year. AMD's chips use technologies such as immersion lithography and strained silicon, both developed jointly with IBM.
IBM added Hitachi to its list of collaborators on Monday when the two companies announced a two-year joint semiconductor research agreement in order to speed the pace of semiconductor innovation. The agreement marks the first time Hitachi and IBM have collaborated on semiconductor technology.
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