Intel filled in some of the missing details on its Silverthorne mobile processor Tuesday, helping explain how it managed to get the power consumption of this chip down under a couple of watts.
Gianfranco Gerosa of Intel presented the company's paper on Silverthorne, its low-power mobile processor destined for the next generation of mobile Internet devices later this quarter, during the International Solid State Circuits Conference in San Francisco. Intel Chief Technology Officer Justin Rattner had already discussed Silverthorne in some detail last week, but the wonky details were laid bare for a roomful of people who are way, way smarter than me.
A few Silverthorne tidbits, however, could be deciphered by those of us who wasted their education dollars on a business degree. This chip is tiny, measuring just 3.1 millimeters by 7.8 millimeters for a die size of 24.2 millimeters squared. By comparison, the dual-core version of Intel's newest Penryn chips for PCs has a die size of 107 millimeters squared. That means Intel can make roughly four times as many Silverthorne chips on a single silicon wafer as compared with the dual-core Penryns. Let's see how much the company decides to charge for it.
The chip will be able to reach 2.5GHz, although Intel is quoting a 2GHz clock speed for the 2-watt thermal design power, or the maximum power consumption that system designers have to take into account when building their devices. It uses a 16-stage pipeline, compared to the 14-stage pipeline used by the Core 2 Duo chips.
Think of a pipeline stage as part of an assembly line: the more stages in the process, the faster it has to run to build something in the same amount of time as a line with fewer steps. Intel's Pentium 4 processor topped out at 31 stages, which allowed the company to crank it up over 3GHz to satisfy the marketing department's proclamation that the only thing us mortal PC buyers understood was clock speed.
Unfortunately for Intel, that wasn't a very sound design. A chip running at that kind of speed runs way too hot, especially as current leakage problems became more pronounced, so Intel designed the Pentium M microprocessor with fewer pipeline stages. It did more work per stage, which allowed it to run slower and cooler. Eventually, those design principles were incorporated into the Core lineup of processors, and Intel got its mojo back.
So it's a bit surprising that its most serious low-power effort to date would have two additional pipeline stages, but Intel got around that problem by switching to an in-order pipeline, and by adding hyperthreading. That combination produced the most efficient performance-per-watt ratings in Intel's internal testing, Gerosa said.
Silverthorne also makes use of several low-power states in which the chip shuts down certain elements of the processor when they aren't required by the software. Intel estimates that Silverthorne will spend 90 percent of its time in deepest sleep state, which it calls C6. Virtually everything gets turned off in C6, and it takes 100 microseconds to wake the chip back up when new processing orders come in, Gerosa said.
As a result, Intel is quoting average power numbers for Silverthorne "in the order of a few hundred (milliwatts)," which sounds like quite the accomplishment. That will be nice for battery life, but it doesn't really matter when it comes to building a sleek device. Anyone who wants to use Silverthorne will have to design a device that can handle the full 2 watts of power that Silverthorne will consume running flat out.
After all, the whole point of Intel's pitch to put x86 chips in mobile devices is that those devices would be able to run Windows and any piece of PC software. While Intel is increasingly pitching Linux for its mobile devices--and keeping a close eye on that other mobile operating system--there are certain tasks that are going to require all the processing power Silverthorne can deliver.
The MIDs that Intel and its partners have shown off using Silverthorne don't look all that different from the older MIDs that haven't sold very well to date. They're still a little too bulky to compete with slicker smart phones from the likes of Nokia, Samsung, and Apple, which are powered by chips designed by ARM for mobile phones.
True competition from Intel in this area probably won't arrive until the Moorestown chip is ready in a couple of years, but Silverthorne is a milestone on that path. We'll start to see if people are interested in MIDs based on the chip by the middle of this year, when we'll also get a true sense of its performance.
Intel is expected to shed light on its processor of the future this week as it plugs along with another design that was once supposed to be its processor of the future.
The chip industry's finest minds will be descending on San Francisco this week for the International Solid State Circuits Conference, and Intel plans to present 14 papers highlighting some of its recent work, said Justin Rattner, Intel's chief technology officer and head of Intel Labs. Chief among them will be its low-power Silverthorne processor, Intel's latest plan to infiltrate the world of handheld devices.
"This is the smallest (x86 instruction set) processor we've built in the last 15 to 17 years," Rattner said, speaking of Silverthorne in a briefing for reporters prior to the conference. Silverthorne is expected to arrive in the second quarter in so-called mobile Internet devices, but it's really a stepping stone for Intel toward a lower-power future.
The ultimate goal for Intel is to design a chip that will fit into the next generation of mobile devices and smartphones, carving out a niche for PC software and programming techniques in a world dominated by chip designer ARM and its partners, such as Texas Instruments and Samsung. With a power consumption range between half a watt and two watts, Silverthorne doesn't quite fit into the appropriate thermal profile occupied by those chips. But it can run any piece of software written for PCs at the performance level achieved by one of Intel's 5-year-old Pentium M processors.
Silverthorne is a departure from the rest of Intel's designs in that it's an in-order processor, as opposed to the out-of-order design used in just about every other chip the company makes. That means pretty much what it sounds like; in-order chips have to process tasks in a defined order, but out-of-order chips can process tasks separately and reassemble a finished product later. Out-of-order means better performance, in-order generally means lower power consumption.
The chip also incorporates a new low-power state, allowing it to essentially shut down in between processing tasks and limit power consumption. And just in case the software industry starts producing more multithreaded applications, Intel added an old friend, hyperthreading, to Silverthorne. Hyperthreading allows Silverthorne to present itself as a dual-core chip to software, even though it only has one physical processing core.
While Silverthorne is considered a huge part of Intel's future, Tukwilla, the other major design being presented at ISSCC, is a remmant of Intel's past. Tukwilla will be the next version of the Itanium processor, which Intel once thought could take over the server industry but has been relegated instead to a high-end niche.
Still, that's a powerful niche. Tukwilla will be the first quad-core Itanium processor, and it will use a whopping 30MBs of cache memory. This is going to be a high-performance (read: expensive) chip for high-end servers, and it will also be one of Intel's first chips that borrows design techniques employed by Intel's rival, Advanced Micro Devices, to great effect.
Tukwilla will use point-to-point connection technology that Intel calls Quickpath to directly link processing cores together. AMD introduced this way back in 2003 with its Opteron processor, and it delivers a significant boost in performance as the chip industry moves into the multicore era. Intel's current designs required signals traveling between two different processor cores to leave, then re-enter, the chip. Quickpath lets those signals stay on the chip, allowing them to travel a shorter distance at higher speeds. That's good.
Tukwilla will also use an integrated memory controller, which is a similar concept. Integrated memory controllers, as the name implies, are integrated directly onto the chip. This allows this vital link between the processor and the main memory to run at the speed of the chip, rather than the slower speeds necessitated by the front-side bus design used by Intel's chips.
Intel eventually plans to bring Quickpath and integrated memory controllers down to its Xeon line of server processors, which go into the vast majority of the world's servers. That will arrive with the Nehalem generation of chips, due out later in 2008.
Intel's researchers also plan to present papers in other areas, such as wireless technologies and memory research. The company has been working on radios that can employ multiple protocols, from Wi-Fi and WiMax to even cellular standards, and it plans to highlight some research in this area. The company is also investigating phase-change memory, one possible way to prepare for the end of Moore's Law by discovering ways to represent the fundamental zeros and ones of computing with something other than a transistor.
These presentations are not for the faint of heart. An electrical engineering degree would be very helpful in deciphering the papers, although not exactly required. We'll be on hand during the week to highlight some of the more interesting presentations, especially Silverthorne, which is a key part of Intel's future plans.
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