September 28, 2006 4:34 AM PDT
Processor, memory may marry in future computers
On Tuesday, Intel showed off an 80-core processor at its developer forum taking place in San Francisco this week and one of the prominent features of the chip is that each core is connected directly to a 256KB memory chip through a technology called Through Silicon Vias, or TSV.
The memory wedded to the processor cores could constitute the entire memory needed for a computer, Intel CTO Justin Rattner told News.com in an interview during the Intel Developer Forum. TSV could be used in a variety of chips, not just the 80-core monster. As a result, computer makers, when building a system, would get their memory when they bought their processors from Intel. They would not have to obtain memory chips separately from other companies like they do now.
"You could buy it as a block," he said.
Back in the 1980s, Intel was one of the largest manufacturers of computer memory, or DRAM, but it got out of the market because of punishing competition from Japan. (The company, however, continues to produce NOR flash memory and a few other types of memory. Typically, these chips are not used in the same fashion as DRAM.)
Wedding memory directly to the processor would have huge performance benefits. Currently, memory and the processor in Intel-based computers exchange data through a memory controller, which moves at a far slower rate than the processor. It's one of the big bottlenecks in computer performance. TSV, which displaces the memory controller, would shuttle data far quicker.
Potential competitive edge
Data coming out of memory also squeezes through an overcrowded port. TSV would effectively open up thousands of ports. Overall, Rattner said, TSV is by far a more notable accomplishment than putting 80 cores on the same piece of silicon.
The processor cores are not restricted to getting memory from the chip wedded to it, added Rattner. The cores are connected to each other through high-speed links controlled by a router integrated into each core. Overall, the prototype 80-core chip has an aggregate memory bandwidth of 1 terabyte per second, meaning that it can shift a trillion bytes per second.
Conceivably, TSV would also put AMD on the hot seat. A good portion of the performance gains AMD achieved with the Opteron chip came from Opteron's integrated memory controller. Intel does not put integrated memory controllers on its chips.
In all probability, Intel would not get back into the business of manufacturing DRAM--it remains one of the most difficult chip markets in which to turn a profit. Nonetheless, TSV would put it back into the business of selling it.
Rattner, however, noted that implementing TSV will take time. The memory chips attached to the 80-core processor are SRAM, a relatively expensive memory that Intel still makes. The next step is to see how well DRAM works with TSV.
Engineers would also have to devise packages that would let the processor and memory live together. The processor typically generates more heat than the memory, which is one of the factors that would have to be considered. Although it doesn't get many headlines, packaging design is a huge challenge for chipmakers.
"It's still in the research stage," he said. "We will do a lot of work with it in the next several years."
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