Holes created through imprint lithography measure 60 nanometers in diameter. In current chips, the average feature size is 90 nanometers, while some of the smallest parts are 60 nanometers.
ALTHOUGH YOUR PICTURES MAY BE TRUE, FROM MY KNOWLEDGE 90 NM REFERS TO THICKNESS OF VAPORIZED "DOPED" MATERIAL THAT SETTLES ON SILICA INSULATE MATERIAL. PERHAPS THIS PROCESS FORMS "MASK" THAT IS "WASHED" OUT AFTER VAPORIZATION, THAT CONTROLS WHERE "DOPED" MATERIAL SETTLES DURING VAPORIZATION, WASHED, THEN NEXT LAYER APPLIED, MASKED, DOPED, WASHED, UNTIL TOTAL NUMBER OF "TRANSISTORS" HAVE BEEN APPLIED. SIGNED:PHYSICIAN THOMAS STEWART VON DRASHEK M.D.
Sure, we have pushed the lithographic boundary to even smaller geometries. Now, ASML want to sell us on the idea of a Microlithography immersion system. Lets take another look at this. Is it better to build 65nm highways for electrons drivers to travel. Or maybe its time to change drivers, photons traveling on highways of light are much earier to build.
SIGNED:PHYSICIAN THOMAS STEWART VON DRASHEK M.D.
- Roadmap to a dead end street
- by ASML burke December 26, 2006 1:35 AM PST
- Sure, we have pushed the lithographic boundary to even smaller geometries. Now, ASML want to sell us on the idea of a Microlithography immersion system. Lets take another look at this. Is it better to build 65nm highways for electrons drivers to travel. Or maybe its time to change drivers, photons traveling on highways of light are much earier to build.
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