March 7, 2006 6:08 PM PST
New Intel quad-core chips are really double duo-cores
The move isn't a major surprise: It's the same approach the chipmaker took a generation earlier when introducing its first dual-core processors. But it does indicate the urgency Intel feels to get products--due to arrive in 2007--to market to stay competitive with Advanced Micro Devices.
"Intel wants to get them out in a hurry," said Insight 64 analyst Nathan Brookwood, likening the approach to building a car with two four-cylinder engines instead of a V-8. "I would assume they have a longer-term plan, probably around 45-nanometer technology, to provide a more comprehensively designed quad-core."
The three quad-core chips--"Kentsfield" for PCs, "Clovertown" for dual-processor servers and "Tigerton" for four-processor servers--all use a manufacturing process with 65-nanometer features. In the second half of 2007, Intel plans to move to a more advanced 45-nanometer process that permits more circuitry to fit on a single slice of silicon.
Pat Gelsinger, general manager of Intel's Digital Enterprise Group, demonstrated Kentsfield and Clovertown at the Intel Developer Forum here Tuesday. Those two chips are due in the first quarter of 2007, spokesman Scott McLaughlin said, but the Santa Clara, Calif.-based chipmaker hasn't commented on when in 2007 Tigerton will arrive.
Senior Intel architect Steve Pawlowski is expected to detail the quad-core approach Wednesday at the conference.
Intel isn't alone in using packaging to squeeze more processors into a single socket and boost server performance. IBM began shipping Power5+ Quad-Core Modules in 2005 using these packaging techniques. HP packaged dual Itanium processors, with an approach called Hondo, and sold them as the mx2 product.
But the technique, which AMD hasn't used yet and won't use with its 2007 quad-core chips, has penalties.
"Having a more intelligent quad-core, as opposed to the dual dual-core, translates to better power usage and, in theory, far better performance," Brookwood said. "The advantages are that you get a higher degree of sharing with caches and buses," he said, referring to high-speed memory and the data pathways that connect the chip to the rest of the system.
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