September 27, 2006 6:20 PM PDT

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Intel is preparing for an era in which its server products will take on many different looks for many different types of customers, according to its server chief.

Different combinations of processors, chipsets and design structures are all on tap for future servers, said Pat Gelsinger, senior vice president and general manager of Intel's digital enterprise group. This would involve supporting different interconnect strategies or memory types, he said.

Intel has regained its footing in the server market this year with the launch of its Xeon 5100 series processors. Although Advanced Micro Devices still holds a significant chunk of that market, Intel has improved the performance of its processors and solidified its future road map with the disclosure of technologies such as its CSI (Common System Interconnect) technology. CSI will allow Intel to connect its future multicore processors directly to each other, and it will also feature an integrated memory controller design like the one that has buoyed AMD's Opteron processor.

But that doesn't mean Intel's older designs will go away, Gelsinger said. "The range of platforms we have to cover with more integrated chipsets and CPUs is increasing," he said. This means Intel will likely introduce new categories of processors and chipsets for specific designs, such as compact blade servers, although plans are still coming together, he said.

For example, Intel has embraced the FB-DIMM, or fully buffered memory, standard for its server processors this year. FB-DIMM allows server designers to pack their systems with more memory modules, but those modules consume more power than the DDR (double data rate) memory used in older servers and by AMD. In the future, Intel will probably support both memory technologies for different categories of servers as part of this "hyper-segmentation" approach, as Gelsinger put it.

Likewise, Intel could have products that use integrated memory controllers for a speedier connection between the processor and memory, as well as chips that keep its current front-side bus design, in which signals have to pass through a bus before they reach the memory. "Between the processor and the chipset, we have to cover more dynamic range," he said.

If Intel understands its markets and customers well enough to segment its products in such a fashion, it could delight customers with products that are tailored to their specific workloads, said Nathan Brookwood, an analyst with Insight 64. It would also be harder for AMD, with less resources than Intel, to follow suit, he said.

But the company runs the risk of confusing customers with too many permutations, and could run into problems if it neglects the "sweet spot" of the server market while designing many different products, Brookwood said.

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Pat Gelsinger, AMD Opteron, Intel, chipset, server

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CSI Good, Current Shared Architecture Bad...
When Intel has to throw 16MB of high speed cache on the processor that should pretty much tell you they have a problem with bus speeds and latencies.
AMD gets around this with Hypertransport and the sooner Intel gets it's own version out the better.
Until then Intel multi-processor systems won't hold a candle to AMD Opteron N-Way systems.
Posted by fred dunn (793 comments )
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