August 12, 2002 9:00 PM PDT
Intel stretching silicon for power
The Santa Clara, Calif.-based chipmaker will use "strained silicon"--in which the atoms in a processor's central ingredient are spaced farther apart than normal--in chips made on the 90-nanometer manufacturing process, according to Mark Bohr, director of process architecture at Intel.
Chips made on the 90-nanometer process, Intel's first products of the nanotechnology era, will also feature new insulating techniques, smaller internal components and other advances. The chip that will succeed the Pentium 4, code-named Prescott, will be the first 90-nanometer chip and will arrive in the second half of 2003.
"By stretching the silicon, we can make the electrons move faster" inside the chip, Bohr said. "The basic effect has been demonstrated on large transistors, but there were always doubts that you could achieve the benefits on small, high-performance transistors."
Tinkering at the atomic level is becoming a daily issue for chip manufacturers. For decades, chip manufacturers have steadily shrunk the size of transistors and chips in accordance with Moore's Law, which dictates that the number of transistors on a chip doubles every two years.
Moore's Law has worked so well, though, that engineers now find themselves butting up against the laws of physics. For instance, the gate oxide on chips made on the 90-nanometer process, which separates the subelements of a transistor, will measure only five atoms across. Technically, these chips can be classified as nanotechnology parts because their components will measure less than 100 nanometers across.
Designing chips that work and can be manufactured profitably at this level requires more leaps of creativity than in the past, especially when it comes to power management, according to designers and engineers. Fast chips generally require greater amounts of energy. Increased electricity, though, can be detrimental to performance.
To navigate the contradictory demands, Intel redesigned the insulating materials, replacing a silicon-based material with a carbon one, between different layers of the chips with the 90-nanometer chips, Bohr said. The chips will also contain seven layers of circuitry, rather than the six of current chips. Stretching the silicon, he added, will increase current flow 10 percent to 20 percent, but increase cost only 2 percent.
Chips made on this manufacturing process will be faster than today's microprocessors, but contain far more transistors. Prototype SRAM (static RAM) memory chips produced by Intel contain more than 330 million transistors in a 100-millimeter square space, Bohr said. About 120 billion transistors will fit on a standard 300-millimeter wafer.
Chips made on the 90-nanometer process will first come from the company's fabs in Oregon and later from facilities in Ireland and New Mexico, which are geared more for mass production.
Although more advanced than the 130-nanometer manufacturing techniques, the 90-nanometer process will allow the company to reuse about 75 percent of today's equipment, Bohr said.
"This ensures that we will have a high-volume manufacturing ramp next year," he said.
The 90-nanometer manufacturing process, though, isn't a panacea. Chips made on this process will be more subject to gate leakage, or random energy dissipation, a phenomenon that can reduce battery life and other problems, Bohr said.
Coming up with a system for manufacturing 65-nanometer chips in 2005 will be even more difficult. The gate oxide, for example, will have to go below five atomic layers, which measures only 1.2 nanometers to begin with. The 65-nanometer generation will also be the last made with conventional lithography techniques. In 2007, the industry will switch to Extreme Ultraviolet (EUV) lithography, developed by a consortium of national laboratories and private companies.
"Shrinking it (the gate oxide) to 65 nanometers is going to be pretty tough," he said.