January 25, 2006 9:00 AM PST

Intel shows test chips made on future processes

The 45-nanometer process is right on time, according to Intel.

The Santa Clara, Calif.-based chip giant has created test chips made on the 45-nanometer process and will likely begin shipping processors, flash, and other chips based on that process in the second half of 2007, according to Mark Bohr, director of process architecture and integration at Intel.

The test chips, produced this month, are static SRAM memory chips containing 153 megabits of memory. The chips contain over a billion transistors and are nearly the same size as test SRAM chips produced by Intel in 2000 on the then-new 130-nanometer process that contained 18 megabits of memory. The memory cells on the 45-nanometer test chips take up 0.346 square microns, compared to 2.45 square microns.

45-nano process

The nanometer measurements refer to the average size of the sub-components of the transistor. A nanometer is a billionth of a meter while a micron is a millionth; a human hair is about 60 to 90 microns in diameter.

Although these are just test chips, the milestone is an important indication that Intel's overall manufacturing strategy remains on track. However, it appears that extreme ultraviolet lithography, a future chipmaking technology championed by Intel, may get delayed.

Every two years, Intel and most other major other chipmakers shrink the size of the transistors embedded in their chips in accordance with Moore's Law. Shrinking the transistors in this manner increases overall chip performance, reduces energy consumption and cuts the manufacturing cost per chip.

By staying on a two-year cadence, a chip manufacturer can gain an advantage over a competitor by coming out with faster, less-expensive chips earlier, or at least avoid losing ground. (Moore's Law is still alive and could persist until around 2020 in its present form, although the time between transitions will likely increase.)

Intel has exploited its manufacturing expertise to turn back rival Advanced Micro Devices in the past. Right now, Intel is producing chips on the 65-nanometer process, while AMD won't come out with these chips until the second half. One of the big questions for 2006 is whether Intel's latest chips and the manufacturing advantage will blunt recent gains from AMD.

The 45-nanometer process could become particularly interesting because many chip designers believe it will be one of the more difficult transitions in years. The power consumption and performance requirements of these chips will be extremely high and chipmakers are being forced to add exotic materials and new structures to their transistors to ensure the chips function properly. Many, for instance, will likely include metal or other materials in the silicon gates and gate oxide, two structures inside transistors.

"It does get a little more challenging every time, but we come up with new technology and tricks to keep things going," said Bohr.

If a company botches the process, it could lead to product delays or recalls. Some chipmakers faced these problems during the transition to 130-nanometer chips when they swapped aluminum for copper for making interconnects--the tiny wires inside chips.

Bohr declined to state what, exactly, Intel is putting into its 45-nanometer process. The company in the past has said tri-gate transistors and new types of gates could be included.

One clear part of the process, however, is that Intel will use "dry," or standard, lithography techniques for 45-nanometer chips. Lithography is the art of drawing circuit patterns on chips through optical and chemical processes. "We are committed to dry lithography for this (the test chips) and manufacturing," said Bohr.

Other manufacturers will adopt immersion lithography, where the silicon wafer is immersed in purified water. This helps focus the light beam from the lithography machine with greater precision. The light beam wavelength from these machines measures 193 nanometers and so it is wider (and has been wider) than the circuits that have been included in chips for years. That challenge--aiming the wavelength in way that makes it narrower than the circuits--helps explain why lithography equipment costs several million dollars.

Intel is considering using immersion lithography for 32-nanometer chips, which will come out in 2009. According to Intel, Extreme Ultraviolet lithography (EUV) is "more likely for 22-nanometer" manufacturing, which starts in 2011.

EUV lithography, which has a light source derived from laser beams developed for the Cold War-era Star Wars program, was slated to go into production on the 65-nanometer process, but it has been delayed several times. In 2003, Intel said it was likely that it would use EUV for the 32-nanometer process that starts in 2009.

4 comments

Join the conversation!
Add your comment
Driving by Braille (Where IS That Wall?)
Room-temperature CMOS will hit the wall long
before 2020. I'd expect the 35 nanometer is
going to be real tough, and 25 nanometer looks
like it's made out of rocks. Here's the logic:

1. As you get smaller, tunneling current increases.
At 45 nm, tunneling current is about 50% of the
total power consumption. Tunneling current
increases exponentially as the dimensions shrink.

2. The easy way to reduce heating in general and
heating due to tunneling in particular is to
lower the operating voltage. Each generation
lately uses lower and lower voltage.

3. There are a lot of process issues with low
voltage operation, such as bandgap matching and
the need to reduce surface states below the
gate threshold voltage, but none of the process
issues are a showstopper. Thermal noise is the
problem.

4. At room temperature, thermal noise is about
0.033 volts (300 degrees Kelvin). If you scale
the voltage below about 0.333 volts, then you
are going to have thermal noise reliability
problems.

My conclusion is that the last room-temperature
chip technology will run at around 0.500 volts,
and will have a nominal feature size of 25 nm.
We can expect it to ship in 2010-2012, at
which time it's game over for the continuing
reduction in the size (and cost) of transistors.

The social and economic effects of the last doubling
will be very interesting to watch.
Posted by (139 comments )
Reply Link Flag
Very informative
Mr. Chapman. You have a vast knowledge on this subject and I will look forward to reading your comments on the future. You may be right about it "hitting the wall" but as in the past I believe we will overcome them. It may take an intuitive leap such as going from tubes to solid state back in the 50's. There are alternatives to silicon on the periodic table that can be used for the substrate material. Perhaps one of these may provide a solution.
Posted by Seaspray0 (9714 comments )
Link Flag
Driving by Braille (Where IS That Wall?)
Room-temperature CMOS will hit the wall long
before 2020. I'd expect the 35 nanometer is
going to be real tough, and 25 nanometer looks
like it's made out of rocks. Here's the logic:

1. As you get smaller, tunneling current increases.
At 45 nm, tunneling current is about 50% of the
total power consumption. Tunneling current
increases exponentially as the dimensions shrink.

2. The easy way to reduce heating in general and
heating due to tunneling in particular is to
lower the operating voltage. Each generation
lately uses lower and lower voltage.

3. There are a lot of process issues with low
voltage operation, such as bandgap matching and
the need to reduce surface states below the
gate threshold voltage, but none of the process
issues are a showstopper. Thermal noise is the
problem.

4. At room temperature, thermal noise is about
0.033 volts (300 degrees Kelvin). If you scale
the voltage below about 0.333 volts, then you
are going to have thermal noise reliability
problems.

My conclusion is that the last room-temperature
chip technology will run at around 0.500 volts,
and will have a nominal feature size of 25 nm.
We can expect it to ship in 2010-2012, at
which time it's game over for the continuing
reduction in the size (and cost) of transistors.

The social and economic effects of the last doubling
will be very interesting to watch.
Posted by (139 comments )
Reply Link Flag
Very informative
Mr. Chapman. You have a vast knowledge on this subject and I will look forward to reading your comments on the future. You may be right about it "hitting the wall" but as in the past I believe we will overcome them. It may take an intuitive leap such as going from tubes to solid state back in the 50's. There are alternatives to silicon on the periodic table that can be used for the substrate material. Perhaps one of these may provide a solution.
Posted by Seaspray0 (9714 comments )
Link Flag
 

Join the conversation

Add your comment

The posting of advertisements, profanity, or personal attacks is prohibited. Click here to review our Terms of Use.

What's Hot

Discussions

Shared

RSS Feeds

Add headlines from CNET News to your homepage or feedreader.