SAN FRANCISCO--Intel and Dell this week showed off servers using the chipmaker's forthcoming high-end "Tulsa" Xeon, a chip that Intel has begun shipping but not formally announced.
The chips were used in an unlabeled Intel server and a Dell PowerEdge 6850 on display here at the LinuxWorld Conference and Expo. Linux is popular chiefly on servers, so Intel, Dell, Hewlett-Packard, Advanced Micro Devices and others with server products are prime sponsors of the show.
Tulsa, a dual-core processor, is the last of the ill-fated NetBurst lineage of x86 chips from Intel. The NetBurst design in recent years was more notable for increases in power consumption than in performance, but it's now been largely replaced by the Core microarchitecture that performs better and uses less electricity.
Each Tulsa processor core has 1MB of level-two cache memory, and the two cores share a whopping 16MB of level-three cache memory, more than any other x86 processor. Cache memory stores instructions and data so the information can be retrieved more quickly than that in main memory.
Tulsa uses 1.3 billion transistors--nearly as many as the 1.6 billion in Intel's new "Montecito" version of the Itanium processor, said Radhika Kunte, an Intel representative at the show. Intel can afford to build large caches better than its rivals, because it has moved more quickly to a new manufacturing process with 65-nanometer circuitry elements, letting more transistors be crammed into a given surface area. Most rivals still are building chips with a 90-nanometer process.
The processor runs at a top speed of 3.4GHz, according to an Intel presentation at the show. Tulsa comes in two variants: one high-performance model that consumes 150 watts of power and one geared for rack-mounted servers that consumes 95 watts.
Tulsa chips fit into servers using Intel's "Truland" platform, a server design that also accommodates the single-core "Potomac" Xeon processors introduced in early 2005 and the dual-core "Paxville" models introduced in late 2005.
Compared with Paxville, Tulsa boosts transaction processing performance by a factor of 1.7, enterprise resource planning software by a factor of 1.4, and e-commerce software by a factor of 2, Intel said.
Sure throw 16 MB of cache at it to make up for the FSB delays caused by the HUB architecture. When are they going to go to another communications channel similar to Hypertransport so that the CPUs aren't sitting there in wait states because of bus arbitration? But then Intel still thinks Itanium is viable so why should anyone expect them to "break away" from the old and make progress. The core architecture is a good start but even there they are still just trying to throw cache at the bus problem. That is why AMD is going to lead them in 4+ way servers for the foreseable future.
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But then Intel still thinks Itanium is viable so why should anyone expect them to "break away" from the old and make progress.
The core architecture is a good start but even there they are still just trying to throw cache at the bus problem. That is why AMD is going to lead them in 4+ way servers for the foreseable future.