August 22, 2006 7:10 PM PDT
Intel readies 'Tulsa' Xeon debut
"Tulsa will be introduced next week at about a 70 percent higher performance rate," compared with its "Paxville MP" predecessor introduced in November, Intel's Jeffrey Gilbert said in a speech at the Hot Chips conference here. His presentation's fine print added more detail, saying the Tulsa launch is scheduled for Aug. 29.
Tulsa, a 3.4GHz Xeon "MP" chip that drops into existing servers with four or more processors, is the last chip to use Intel's now all-but-phased-out NetBurst architecture. Intel prefers to direct attention to its new Core architecture--both in terms of performance and performance per watt--but Gilbert adamantly defended the Tulsa design.
"At introduction, Tulsa will have in its market segment the leading performance and leading performance per watt on MP platforms. It's a good part," Gilbert said.
Intel could use a shot in the arm for server processors. Although it's still dominant, rival Advanced Micro Devices' Opteron has won a major place in all of the big four server manufacturers' product lines. Even as Intel fights back with its "Woodcrest" Xeon for dual-processor servers, longtime loyal ally Dell added AMD servers into the mix and IBM expanded its products to include a full range of Opteron systems.
Intel began shipping Tulsa chips for revenue this quarter, Chief Executive Paul Otellini said in July, bringing the products to market a quarter earlier than planned.
Tulsa is compatible with two predecessors introduced in 2005, the first-generation "Potomac" model and the dual-core "Paxville MP." Where those were manufactured using a process with 90-nanometer electronic circuitry elements, Tulsa can accommodate more transistors in comparable surface area because it uses Intel's 65-nanometer manufacturing process. (A nanometer is a billionth of a meter.)
The major use for all that new circuitry is a large amount of cache memory that stores data for faster access than main memory can provide. Tulsa has 16MB of level-three cache, more than any other chip except the top-end "Montecito" Itanium with 24MB.
"A large cache hides a multitude of sins," Gilbert quipped.
In Tulsa's case, the large cache means that data is more readily at hand, lightening the communication load on the front-side bus that joins the chip to the rest of the system and decreasing the effective memory communication delay to a third of Paxville's, he said.
The performance increase on the TPC-C test from the Transaction Processing Performance Council is significant. Potomac systems could perform 115,000 transactions per minute, and Paxville increased that to 188,000, he said. Tulsa will push the number about 70 percent higher, which would translate to about 320,000 transactions per minute.
Adding more cache wasn't without cost, though. Despite the more advanced manufacturing process, Tulsa measures 424 square millimeters compared to 299 for Paxville and 354 for Potomac. The larger a chip, the fewer can be cut from a single slice of silicon, raising manufacturing costs.
To reduce chip size, Intel had to sacrifice the amount of faster level-two cache, dropping from 2MB to 1MB for each core on the chip. "That's the wrong direction, but it didn't seem to hurt our platform overall," Gilbert said.
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