August 22, 2006 7:10 PM PDT

Intel readies 'Tulsa' Xeon debut

PALO ALTO, Calif.--Intel will introduce its top-end "Tulsa" Xeon processor next week, one of the chip's senior engineers said Tuesday, promising a significant performance boost for servers handling database work.

"Tulsa will be introduced next week at about a 70 percent higher performance rate," compared with its "Paxville MP" predecessor introduced in November, Intel's Jeffrey Gilbert said in a speech at the Hot Chips conference here. His presentation's fine print added more detail, saying the Tulsa launch is scheduled for Aug. 29.

Tulsa, a 3.4GHz Xeon "MP" chip that drops into existing servers with four or more processors, is the last chip to use Intel's now all-but-phased-out NetBurst architecture. Intel prefers to direct attention to its new Core architecture--both in terms of performance and performance per watt--but Gilbert adamantly defended the Tulsa design.

"At introduction, Tulsa will have in its market segment the leading performance and leading performance per watt on MP platforms. It's a good part," Gilbert said.

Intel could use a shot in the arm for server processors. Although it's still dominant, rival Advanced Micro Devices' Opteron has won a major place in all of the big four server manufacturers' product lines. Even as Intel fights back with its "Woodcrest" Xeon for dual-processor servers, longtime loyal ally Dell added AMD servers into the mix and IBM expanded its products to include a full range of Opteron systems.

Intel began shipping Tulsa chips for revenue this quarter, Chief Executive Paul Otellini said in July, bringing the products to market a quarter earlier than planned.

Tulsa is compatible with two predecessors introduced in 2005, the first-generation "Potomac" model and the dual-core "Paxville MP." Where those were manufactured using a process with 90-nanometer electronic circuitry elements, Tulsa can accommodate more transistors in comparable surface area because it uses Intel's 65-nanometer manufacturing process. (A nanometer is a billionth of a meter.)

The major use for all that new circuitry is a large amount of cache memory that stores data for faster access than main memory can provide. Tulsa has 16MB of level-three cache, more than any other chip except the top-end "Montecito" Itanium with 24MB.

"A large cache hides a multitude of sins," Gilbert quipped.

In Tulsa's case, the large cache means that data is more readily at hand, lightening the communication load on the front-side bus that joins the chip to the rest of the system and decreasing the effective memory communication delay to a third of Paxville's, he said.

The performance increase on the TPC-C test from the Transaction Processing Performance Council is significant. Potomac systems could perform 115,000 transactions per minute, and Paxville increased that to 188,000, he said. Tulsa will push the number about 70 percent higher, which would translate to about 320,000 transactions per minute.

Adding more cache wasn't without cost, though. Despite the more advanced manufacturing process, Tulsa measures 424 square millimeters compared to 299 for Paxville and 354 for Potomac. The larger a chip, the fewer can be cut from a single slice of silicon, raising manufacturing costs.

To reduce chip size, Intel had to sacrifice the amount of faster level-two cache, dropping from 2MB to 1MB for each core on the chip. "That's the wrong direction, but it didn't seem to hurt our platform overall," Gilbert said.

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8 comments

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Tulsa is a good part from retarded Intel engineering
Intel is so obsolete, it has become a joke. 8 Tulsa cores share a 667MHZ bus, each core gets 80MHZ, less than that of a 80486.

Paul O should fire all Intel engineers. They are totally retarded.
Posted by sharikou (106 comments )
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Core 2 is most impressive chip on market
Maybe Intel has been second to AMD for a while but Core 2 Duo is currently the most impressive CPU on the market. It is a breakthrough design.

Compare Intel's Core 2 Duo to everything else here: <a class="jive-link-external" href="http://www23.tomshardware.com/cpu.html?modelx=33&#38;model1=430&#38;model2=501&#38;chart=176" target="_newWindow">http://www23.tomshardware.com/cpu.html?modelx=33&#38;model1=430&#38;model2=501&#38;chart=176</a> and you will see it is in a league of its own.

Core 2 has power consumption levels almost in line with AMD and way better than the last gen P4.

Core 2 has 85 million fewer transistos than the Pentium D (source <a class="jive-link-external" href="http://anandtech.com/cpuchipsets/showdoc.aspx?i=2795&#38;p=1" target="_newWindow">http://anandtech.com/cpuchipsets/showdoc.aspx?i=2795&#38;p=1</a>)

Core 2 has a die size 13% smaller tham than the Pentium D and 22% smaller than the Athlon X2.

Even the $316 2.4GHz Core 2 Duo E6600 is faster than anything AMD has on the market (i.e. for $900), and it has been overclocked to nearly 4GHz with air cooling.

The $183 1.86 Core 2 is faster in most benchmarks than $1,000 3.73G Extreme Edition 965.

AMD is not going to have an answer to Core 2 till the K8 architecture, and by then Core 2 will be more refined.
Posted by Dachi (797 comments )
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Incorrect
While I'm no fan of the Tulsa MP processor (one huge omission in the story is the power consumption numbers for the beast, which can top 130W easily in high-end parts), but Tulsa MP systems have two busses to the northbridge. Therefore only four cores per bus and the busses run at either 667MHz or 800MHz; worse case, each core gets 166MHz... but there lies the reason for the hefty amount of cache.

Yes, Tulsa MP is a stop-gap solution until Intel can get a Core 2 version of a Xeon MP spinned out and is still behind the Opteron 800/8000-series in several ways (particularly in memory access and power consumption).
Posted by questionlp (3 comments )
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Intel Hasn't Addressed n-Way Servers Yet...
This is the Opteron's strength because of Hypertransport it can communicate to other processors in multiple processor servers without having to go through the front side bus.
This is why the Opteron is optimal in 4 way and higher servers. Intel's processors depend completely on the common bus to communicate between EVERYTHING and their HUB architecture is outdated for anything over 2 way servers and that is when they are using their 2 bus chipset which still pales incomparison because arbitration is still required in the chipset itself.
WHY, WHY, WHY do you think Intel is increasing the cache to 16MB? So it does not have to go out to the bus as often or so they hope. When Intel does this you have to realize that they inderstand where the bottlneck is but fail to change their ways and do anything about it. God forbid they incorporate Hypertransport and actually get rid of the bottleneck.
Intel's culture is one of NIH (not invented here) and if it's NIH then they will not use it no matter how superior the technology. So we saw with RAMBUS, So we saw with the mixed 32/64 bit chips as Intel only responded when AMD made headway when they released their x86 64 bit chips. Otherwise they would be forcing Itanic down their partners throats for 64 bit apps. With the current series of Core architecture Intel has finally made some headway into the single CPU market but they have a long road ahead of them for multi-way servers and the longer they hold onto their NIH strategy the more market share AMD is going to gain in the higher end server market. When it comes down to it a desktop processor can deal with as a single processor server CPU.
Keep it up Intel, you made one giant step and now it looks as though you're going to spend the next few years being complacent again.

Fred Dunn
Posted by fred dunn (793 comments )
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