Intel names Merced chip Itanium

Itanium--think "Titanium" with a slight regional accent--will be the official name of Intel's Merced processor, and the company will provide more details on the chip's microarchitecture at the Microprocessor Forum in San Jose, California, tomorrow.

The name Itanium was chosen to "reflect the strength and performance of the processor," said Jami Dover, vice president of marketing at Intel. Sausalito, California-based Lexicon, which also coined the chip names Celeron and Xeon, came up with the name, she said.

Itanium, due toward the middle of next year, will be the chipmaker's first 64-bit processor, which means that the chip can process information in 64-bit chunks. Current Intel processors work with 32-bit chunks.

The processor will allow Intel to provide the building blocks for servers that compete against the expensive "big iron" servers currently sold by Sun and others. Itanium-based systems will largely be targeted to e-commerce applications and to Internet service providers.

Although Intel has not officially released the speed or price of the chip, it will provide details about the internal structure of the chip tomorrow, according to Steve Smith, vice president and general manager of the IA-64 division. If anything, the structure of the chip makes it apparent that the processor will indeed be more powerful than any previous Intel processor, he said.

The Itanium will be capable, theoretically, of performing at six gigaflops, or performing six billion operations per second, Smith said. The chip will include 4 integer units and 2 floating point units, two internal structures integral to mathematical calculations.

In addition, Itanium will come with up to 4MB of secondary cache memory, Intel said. Cache serves as a data reservoir for the processor and enhances performance. Current Intel Xeon chips top out at 2MB of cache. In its package, the chip is slightly smaller than a 3 x 5 index card.

To complement the chip, Intel will also produce the 460GX chipset, which will work with standard 100-MHz memory, the company said. Initially, the Itanium will not be geared to work with next generation Rambus memory. Server builders typically are more concerned with the amount, rather than the speed, of memory, and using standard memory initially will allow them to pack much more memory into their systems.

Intel is currently having trouble with its 820 chipset, which is the first to use Rambus memory.

More "Coppermine" details
Intel will also use the Microprocessor Forum to provide more details on its "Coppermine" Pentium III processor, which is expected on October 25. Coppermine differs from current Pentium IIIs in that it will contain 256KB of integrated secondary cache on the same silicon as the processor. Current Pentium IIIs come with 512KB of cache, but the cache is on separate chips.

Although smaller, the integrated cache will boost performance and help Intel close the performance gap between the Pentium III family and AMD's recently released Athlon chips. Overall, Intel states that its own benchmarks show that Coppermine outperforms standard Pentium IIIs in 3D tests by 13 to 23 percent.

The new Coppermines are expected to run at 700 MHz, with a 733-MHz version coming soon after. Mobile versions of the chip running at 500 MHz will also be released.

Coppermine processors will also come with a 133-MHz system bus, which is the main conduit between the processor and the rest of the computer. Most Intel system buses today run at 100 MHz. Later, Coppermine chips will work with Rambus memory.