Now that he's in charge of Intel's biggest and most important division, the Digital Enterprise Group, he's responsible for both the Core and Itanium processor lines.
In London for a conference on power management in data centers, Gelsinger sat down with CNET News.com's sister site ZDNet UK to discuss a wide range of issues, in particular how Itanium is converging with the new Core architecture, how quickly the developing world is catching up in supercomputing, and the debate he doesn't expect to see concluded before 2020.
Q: How are you getting on with moving developments in the Core architecture onto the Itanium?
Gelsinger: Itanium used to be a shared development process between HP and Intel. We've consolidated that with the agreement we announced two years ago, which allowed us to integrate all of the Itanium development activities and get a consistent development methodology. Since that move, we've basically hit all of our timings--the first Montecito slip aside, we're back on track.
Part of that on-trackness means we can leverage the same circuit design libraries, process technologies, all of those other things we were not doing a good job with before. So going forward, the circuit techniques, the power-management technologies, all those sorts of things are much better leveraged. The first realization of that is Tukwila (quad-core Itanium) in late 2008, the next step in the product family, where we move to common system architecture elements, as well as full alignment on design tools and process. It's still a different microarchitecture, a different instruction set, still aiming at a different market segment than the core of our product line. I'm driving for more convergence in Poulson (post-Tukwila Itanium) and beyond.
Presumably the cache architectures are converging as you move to a common bus?
Gelsinger: Yep. You just get more and more, and some of the differences that we had before weren't for good reasons, and we're bringing those together, so I'm pretty happy that this gives us much better leverage for the R&D investments. As you move to a common systems architecture, it's much better investment for the customers as well. HP can say: "I can do a platform development, so I have a lower-end Xeon platform that can be used to bring Itanium lower in my product line," so you start to get that not just in our developments, but also in the OEM (original equipment manufacturer) developments.
Do you see convergence continuing to the point where there's one chip with a mode bit (making it compatible with Core and Itanium)?
Gelsinger: I don't see it getting that far, but I am driving these things to be as common as possible.
How's the heterogeneous versus homogeneous multicore debate going within Intel?
Gelsinger: I expect that debate to be going until 2020, and I expect--in my crystal ball--different market segments coming to different conclusions in that discussion. You can clearly envision--and this is an easier discussion to have after IDF (Intel Developer Forum) than it is today, so we'll have to have the next installment of this discussion after April 17--but you can see the lower end of the product line having homogeneous, little cores.
You could imagine the midrange of the product saying: "We need some big cores, for performance, but little cores are more efficient for certain portions of the workload." You can imagine some embedded applications where you have big cores but with some special-purpose cores for other, specific applications, maybe XML acceleration or packet processing or other things like that--a range of building blocks, from little cores to big cores to special purpose cores. You now have a fabric of choices to mix and match for the market segment.
Won't you need some complicated design and verification tools to maintain a large library of very complex cores? Is that a limiting factor in the speed at which you can develop them?
Gelsinger: Sure. Verification is already a limiting factor. That ends up being the rate-limiting portion of new products coming to market. That continues to be the case looking forward, although I do expect that to be helped by formal verification methods and formalization of on-die interconnect. What happens is that near the CPU is a great sucking sound.
Some CPUs suck more than others.
Gelsinger: In multiple respects...Anyway, the CPU starts hauling everything in. What you saw as the system architecture yesterday, tomorrow is the on-die architecture. As that starts to come together, some of these formalizations, interfaces, etc. become part of the die. It's not that far away until you'll see the one-chip blade.
You've just announced a new transistor design on the 45-nanometer process. How far will it take you before you have to have another look at the transistor architecture?
Gelsinger: There's the structure of the transistor and the materials of the transistor. The materials we just announced; the move to hafnium and metal gate is good for quite some time. We don't expect to change the material structure for a while--improve it, tune it, perhaps, but it's going to last us for several generations.
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