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Called "Dual Stress Liners," or DSL, the technique will ideally eliminate much of the complexity involved with strained silicon. Chips containing DSL are quietly already being sold, but both companies will start to use it in chips built on their 90-nanometer production processes in the first quarter, which will lead to greater proliferation.
According to early data, DSL improves transistor performance in its chips by 24 percent, but incorporating it does not decrease the number of good chips that come out of a wafer, meaning that it should be relatively inexpensive to adopt.
DSL also will heat up the processor-technology arms race between IBM and AMD and rival Intel. Intel uses a form of strained silicon with similar characteristics in its current 90-nanometer chips on sale now and will insert an enhanced version of strained silicon on its 65-nanometer chips coming toward the end of the year. (The nanometer measurements refer to the average feature size on the chips; a nanometer is a billionth of a meter.)
Its enhanced material will improve performance in its transistors by 30 percent, Intel says.
IBM, AMD and Intel will all provide details on their straining technologies at the International Electron Devices Meeting in San Francisco this week.
Strained silicon involves arranging the atoms in a layer of silicon in a manner that will allow electric carriers to move faster from one end of a transistor to another. In turn, faster transistors--the on/off switches inside chips--can lead to better chip performance and/or lower power consumption.
"The whole industry is looking for ways to make transistors switch faster," said Nick Kepler, vice president of logic technology development at AMD.
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