Chipmakers aim to unclog data paths

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Who needs this sort of computing power? Firewalls, Agarwal said. The avalanche of spam has created a market for networking devices that can more accurately and thoroughly examine data packets and toss out the unwanted ones. Video-on-demand systems, high-definition video, security systems and video conferencing are also growing and will require faster systems.

Ultimately, these kinds of computing tasks are also going to downgrade the role of processing cores in the computing world.

"The processor is becoming more and more anonymous, and the system is becoming more and more important," Agarwal said. "The processor is the new transistor."

Who is this guy?
Agarwal has been a fixture in high-end chip designing for years. While a professor at Stanford in the early 1980s, he worked on the design of the MIPS chips, which helped Silicon Graphics achieve its gains back then. (Stanford University President John Hennessy was the leader of that project.) In 1991, Agarwal was a co-author on a paper presented at Hot Chips on Sparcle, a Sun processor that touted multithreading.

In 1996, he started to work on integrating mesh networking into chips. Tilera was founded in 2004.

So far, the company has raised $40 million from Bessemer Partners, Walden International and VTA, the venture capital arm of Taiwan Semiconductor Manufacturing Co. TSMC also will manufacture the chip.

The architecture behind the Tile64, however, may only be adequate for cutting-edge chips for a decade or so, Agarwal theorized. His lab at MIT--as well as those at Intel, Luxtera and a number of other companies--are already examining ways to replace the metal connections between chip cores with faster, cooler, optical fibers.

Shrinking optical components so that they can connect chip cores will take time. The technology will likely be used to connect boards and components. Still, the mushrooming growth in cores may demand it.

MIT's research into inter-core optical connections "may see the light of day in 12 years--maybe 2016, 2017," Agarwal said. "When we want to go to 4,000 or 5,000 cores, we may need other technologies."

[cybervigilante]

but what about quantum microstructures?

My dog just pooped

[grey_eminence]

Future will be challenging

A whole new communication, data storage, and
software infrasture will need to be created
to handle the data bandwith.

[TomMariner]

Tip of the Iceberg

And all of this is essentially done in two dimensions! Think of what happens to processor density when we can grow up and down as well as side to side.

Now the burden falls to the software jocks. We have two generations worth of programmers who think sequentially, that one task follows another. There are a merry band of us who are forced to think in terms of multiple streams operating in real time. But even that abilty is a pale imitation of the ingenuity we are going to have to conjure up to take advantage of the huge gift (and challenge) the chip designers are giving us.

Just wait until processors are thought of in terms we now apply to memory -- "How many tera-procs are you running"?