January 26, 2007 9:01 PM PST
Chip companies entering their metal period
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But as companies make smaller transistors, plugging leaks becomes a huge problem. As gate dielectrics get thinner and thinner--currently about five atoms wide--electrical current can leak out, creating a situation in which the transistor isn't really on and isn't really off. Leaky current also creates excess heat and causes all sorts of system problems.
The enormously expensive chipmaking process means that companies tend to stick with materials they know, said Dan Hutcheson, president of VLSI Research. Finding new materials that can control leakage, operate faster than the older materials and endure repeated manufacturing by the millions is quite a challenge.
"We haven't changed a material in the transistor since the '60s," Hutcheson said.
Switching to a combination of metal gates and high-k dielectrics appears to be the answer to controlling leakage and keeping Moore's Law alive. High-k dielectrics can be made thicker than silicon dioxide dielectrics, decreasing current leakage and giving chip designers another couple of generations in which they can continue to make transistors smaller.
"You've taken what was a layer too thin to scale, and made a layer whose electrical properties are what you need, but the difference is it's vastly thicker," IBM's Meyerson said. "You can then scale this into the future."
But high-k materials can't really be used with conventional silicon gates, Intel's Bohr said. The silicon gate wouldn't be able to switch between states as quickly as usual because of problems in the interaction between the silicon gate and the high-k dielectric. So, Intel identified metals that it can use for both positive and negative transistors to solve that problem and make sure the gates continue to switch very quickly. IBM and AMD will likewise use metal gates with the new dielectrics, Meyerson said.
The exact combination of the metals and the high-k gate dielectric is key, Bohr said. The dielectric is based on the element hafnium, but he declined to specify the exact recipe used to build the new transistors. "Identifying the right combination is a very significant accomplishment, and we're not going to give that away for free," he said.
IBM also declined to comment on the specific nature of its high-k material, but it has published research in the past about using hafnium for this purpose, Meyerson said.
Intel first used the combination of metal gates and high-k dielectrics on the test SRAM (static RAM) chips it built using its 45-nanometer technology, Bohr said. The dielectric must be built using atomic-layer deposition, he said, meaning that a machine must deposit the dielectric just one atomic layer--the width of a single atom--at a time.
The companies diverge, however, when it comes to the methods they will use to build these transistors. IBM and AMD plan to use a technique called immersion lithography, in which the lines on the chip are etched while it is immersed in purified water. Intel is sticking with its current techniques, but might consider using immersion lithography for its 32-nanometer chips, Bohr said. Likewise, Intel will continue using its 193-nanometer dry lithography tools, bucking a trend toward immersion lithography pursued by companies like IBM and AMD.
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