February 12, 2004 9:00 PM PST

Big Blue gives 90-nano boost to PowerPCs

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IBM has begun to produce PowerPC chips using a new manufacturing process that promises to improve their speed and energy efficiency.

The tech giant plans to announce on Friday that it has started mass production of PowerPCs on the 90-nanometer process, which refers to the average feature size on the chips. (A nanometer is a billionth of a meter.) The PowerPC 970FX, which is used inside IBM's blade servers and Apple Computer's Xserve G5 server, is the first processor to be made with this manufacturing method.

Big Blue is expected to describe a 2.5GHz version of the chip made on the 90-nanometer process at the International Solid State Circuits Conference (ISSCC) in San Francisco next week. PowerPCs on the market today, produced on a 130-nanometer process, top out at 2GHz.

To make the new PowerPCs, IBM is combining layers of silicon on insulator (SOI) and strained silicon. Together, the two technologies allow manufacturers to improve energy efficiency or performance: They can either make processors that run as fast as current models but consume far less power; or they can produce chips that use the same amount of power but run at higher clock speeds.

Reducing power consumption is greatest challenge facing chip designers, said Intel Chief Technology Officer Pat Gelsinger and other industry figures. Different manufacturers are adopting different techniques to solve the problem, which has a couple of aspects. First, designers have to figure out how to get all that electricity into a shrinking piece of silicon. Second, the heat generated by this can cause malfunctions.

IBM has long been the primary proponent of silicon on insulator technology, which functions like a sponge. An insulating layer sits below the transistors inside a chip and decreases power consumption by preventing electricity from leaking out.

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Strained silicon, by contrast, removes layers and ridges in silicon, which in turn allows electrons to move faster. The concept, which involves inserting large germanium atoms deep in a wafer, was initially introduced in the late 1980s and early 1990s, but was mainly dismissed.

"In '85, '86 or '87, if you proposed this, people would die laughing," said Bernard Meyerson, chief technology officer at IBM's Technology group, in an interview last year.

Intel came out with its first chips containing strained silicon earlier this month, when it released Prescott. Intel, however, has not adopted silicon on insulator technology.

For future chips, AMD and other companies are looking at switching from silicon to metal for the gate oxide, a thin layer that helps control the flow of electrons in a transistor.

 

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