Newsmaker: Beyond Opteron

In his previous business incarnations, Phil Hester spent more than two decades at IBM, then founded a server manufacturer called Newisys. But as the (relatively) new chief technology officer at Advanced Micro Devices, that impressive resume will likely be put to the test.

Appointed in September, Hester is taking on full force the future of AMD's processor designs. He replaced Fred Weber, a man who many credit with the development of AMD's Opteron chip, a key piece in the Sunnyvale, Calif.-based chipmaker's turnaround.

CNET News.com recently spoke with Hester about AMD's plan to offer quad-core processors by 2007; migrate to DDR2 (a computer memory technology that, as of 2005, is becoming the mainstream standard for personal computer memory); and his vision of the next generation of Opteron and Athlon processors, including building the company's ecosystem by licensing its technology.

Q: Is it true that AMD is looking at licensing parts of its architecture?
Hester: The idea has been around for a while but it relates to understanding what our direct customers and the end customers want to do. The idea is to selectively license the coherent HyperTransport technology (a chip-to-chip interconnect supported by AMD and primarily used on a computer system board in distances up to 24 inches).

Isn't this the technology that you have been promoting for years as a better alternative to Intel's front-side bus systems or its upcoming Common System Interconnect?
Hester: Exactly.

And you're going to license that to other people?
Hester: Right. So the example I'd give you is in the high-performance tactical computing area, where people like Cray and others would like to do vector floating-point units.

Being able to do that requires a co-processor, or attached processor elements that would attach into a standard system. We don't have any finalized plans yet, but if you look at the workloads in the data center, you're starting to see applications where, if you could accelerate XML and Java, a number of the vertical applications would perform significantly better. So instead of trying to build a machine that's just aimed at workloads, you can think about the attached processor or co-processor that works in conjunction with our AMD64 architecture to accelerate those workloads.

They've canceled a heck of a lot more projects than we've canceled. What I hear is (Intel) is showing stuff that they're not going to ship for six to nine months and then comparing it to our stuff that's shipping today.

Can you paint a picture of how it would look on the motherboard?
Hester: The simplest way to think about it is to build an eight-way symmetric multiprocessor system based on AMD64 processors such as Opteron. Think about the ability to replace one of those with a specialized engine. This chip is really aimed at running a specific workload like vector floating-point or XML or Java.

Is that technique possible today without letting that partner have knowledge of how AMD uses HyperTransport?
Hester: No, you would have to have detailed knowledge in the form of a license for the coherent HyperTransport.

How is this going to be a good competitive advantage for AMD's strategy?
Hester: This is the concept of a friendly ecosystem that today, if you want to go build a specialized system, you really have to build all of it. Instead of building all the hardware infrastructure and the software infrastructure to support it, the idea here is that it's a lot less development expense and, in my opinion, a lot easier to leverage the standard software infrastructure that's there.

Is this a radical shift in AMD's strategy?
Hester: Yes and no. The nice thing about this is the AMD64 design is a reliable, high-volume cross-platform. The ecosystem is in place to support that already because it's fully compatible over the Linux and Microsoft software out there. It's also nondisruptive as you kind of move upstream. That is not the case with Itanium, for example.

I think AMD now is at the point that the base hardware level is very competitive, and the question for us now is, "Okay, you have a great platform; now what do you do?" And so my bias is, once you got a base platform, you want to effectively then build on that very quickly at all levels. There'll be elements of that or hardware-enabling technologies like a license to coherent HyperTransport. There'll be work we'll do with Microsoft and the software Linux community to deal with things like ease-of-use or reliability features and recovery, and virtualization partitioning. So to me, it's the next level of focus in the industry, beyond just the raw silicon level.

Let's talk about AMD's raw silicon level. Opteron and Athlon chip architectures are based on your K8 designs, previously called Hammer. Is there a K9--or Hammer 2--in the works?
Hester: There's kind of two separate discussions related to that question. One is the software-visible instruction set architecture, the ISA. The second thing is the internal architecture of how you actually implement that in silicon, and so those two things are separable.

Let me give you some examples. If you look at what we're doing around virtualization and security on Pacifica (which will let computers run multiple operating systems) and Presidio (a security technology that ensures separate processes can't interfere with each other), those were instruction set architecture (ISA) extensions. Obviously, hardware changes are needed under the covers to implement that, but there are those who have done so largely around the microarchitecture code that exists today. So, AMD's kind of manufacturing in strategy is roughly every quarter we've got a higher performance transistor and so you kind of keep the same underlined microarchitecture and incrementally improve new manufacturing technology. So, the structure of the microarchitecture largely stays the same.

Then there is a brand new core design that has to be fully backwards compatible with the old instruction set architecture. Then you can also choose to introduce new instruction set extensions at the time of that new core. So, what you typically see is a core that lives--depending on the market segment--two to four years, and so then you want to time the introduction of a new core with major changes that you need at the system level.

More Newsmakers

[sharikou]

AMD is indeed 5 years ahead of INTEL

INTEL's next generation Conroe CPUs are based on 1995 Pentium Pro+some hyperpipelining stuff, even Business Weeek is not amused. INTEL's Dempsey with dual FSB is no more than a copy of the 2001 Athlon MP. http://sharikou.blogspot.com/2005/12/intel-bensley-dempsey-blackford-copies.html

Further Dempsey is only a 2P chip. Once AMD goes quad-core, INTEL will be completely wiped out of the server market, as we know, INTEL's FSB based archtecture can't scale above 2 cores per bus. Dempsey is only good for 2P 4 core computing. With dual core, Dempsey's two buses will make INTEL closer to AMD on 2P performance (right now there is a 50% disadvantage for INTEL). However, once AMD moves to quad-core, 1 single AMD CPU will be faster than two INTELs. INTEL can't get back by going quad-core, because FSB limitation prevents it from scaling up. At that point, only the most die-hard INTEL fans will buy INTEL servers.





http://sharikou.blogspot.com/2005/12/eric-and-paul-conversation.html