December 4, 2006 9:00 PM PST

AMD launches its 65-nanometer chips

Advanced Micro Devices has started to ship chips made on the 65-nanometer process, as the manufacturing spat with Intel heats up.

AMD chips made on the 65-nanometer process will consume about 30 percent less energy than the same ones produced on the 90-nanometer process when running at the same speed. In the first chips shipped on this process, virtually all of the benefit comes in reduced power consumption, said Nick Kepler, vice president of logic technology development at AMD.

Later, the company will balance energy conservation and performance gain, depending on what the designers want to achieve with various desktop, notebook and server chip designs, he said.

The improvements in part come because AMD is straining the silicon in the transistors inside its chips with a silicon germanium film to improve performance, a first for the company. Intel already uses silicon germanium extensively.

Straining silicon improves the performance of transistors because the larger germanium atoms slightly rearrange the silicon atoms and thereby allow electrical carriers to move more rapidly. In the N-channel transistors, which carry negative electrons, germanium spreads out the lattice of the silicon; electrons flow more freely, sort of like a deer running through a forest that's been thinned of trees. In P-channel transistors, which carry positive charges, the germanium compresses the silicon atoms.

"We planned it (silicon germanium) all along with 65-nanometer, but we were prepared to pull the plug on it if it didn't add up to a benefit," Kepler said. "Adding embedded silicon germanium is probably the biggest change."

Creating strain
To create strain in its existing 90-nanometer chips, AMD (and IBM) inserted a technology called Dual Stress Liners.

AMD's 65-nanometer chips will still include Dual Stress Liners, but also include silicon germanium on the P-channel transistors. The N-channel transistors, meanwhile, will get additional strain from something called Stress Memory Technology, or SMT. With SMT, AMD inserts a film into the N-transistors and then eliminates it: although gone, the earlier existence changes the structure enough to create a strain. (AMD outlined these changes at a conference in 2005.)

SMT, Kepler added, is not a variant of another strain technique first discussed by IBM, which involves inserting and then evaporating the germanium layer.

The first chips produced by AMD on the new process will be desktop chips. Notebook and server chips will come in the relatively near future.

Intel and AMD are in the midst of a manufacturing battle. Intel first began shipping 65-nanometer chips in October 2005. Chips made on the 65-nanometer process generally provide more performance and/or consume less power than those made on the older 90-nanometer process. (The nanometer figure refers to the average size of features on the chip; a nanometer is a billionth of a meter.)

Chips popped out on the more advanced processes also cost less to produce. Intel's 14-month lead in manufacturing has been one of the primary reasons it has been able to undercut AMD in some segments.

Up next: 45 nanometers
By moving into production with its first 65-nanometer chips, AMD can start to try to erode that advantage. By the middle of next year, all of the chips coming out of AMD's Fab 36 in Dresden, Germany--one of the two fabs AMD has there--will be only 65-nanometer chips.

Kepler also reiterated the company's goal of shipping chips on the 45-nanometer process in 18 months, a shorter than normal time period between manufacturing nodes. If successful, this will cut Intel's manufacturing advantage to about six months to seven months.

But it won't be easy to do. The 45-nanometer transition is expected to be more complex than the 65-nanometer transition. Both AMD and IBM are committed to adopting immersion lithography--a technique in which the silicon wafer is immersed in purified water to better focus the light beams that "draw" circuits on its surface--for 45-nanometer manufacturing. No one has moved into mass manufacturing with this technique yet. Intel will not adopt it for 45-nanometer manufacturing.

Other structures will have to be added to 45-nanometer manufacturing as well.

"Eighteen months to 45 (nanometers) is tough but doable," Risto Puhakka, an analyst at VLSI Research, said in an e-mail. "Intel is concerned about the maturity of immersion lithography in their roadmaps...AMD is ramping 45 (nanometers) later, which gives immersion time to mature, so in that sense the immersion is easier to choose."

While AMD is now one of the premier manufacturing outfits in the world, it still sometimes hits delays. The company shipped its first 90-nanometer chips in August 2004. Thus, the 90- to 65-nanometer jump took 28 months. Some analysts expected AMD to come out with 65-nanometer chips toward the middle of 2006.

The complex jump from 130 nanometers to 90 nanometers took even more time. AMD was originally supposed to come out with 90-nanometer chips at the end of 2003. Intel had delays too, but has kept closer to the two-year timetable for transitions outlined by Moore's Law.

One thing that could make the transition to 45 nanometers easier for both companies is that the transition won't likely be as radical as it could have been. At one time, both AMD and Intel contemplated doing things like coming out with multiple gate transistors and changing the basic materials in their transistors at 45 nanometers. Now these changes will wait for further transitions.

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silicon, transistor, manufacturing, nanometer, AMD

 

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