February 6, 2006 5:41 PM PST

AMD, Intel unwrap their latest server chips

SAN FRANCISCO--In the world of server chips, Intel is touting performance while AMD is talking up power.

The rivals unfurled details of their next server chips at the International Solid State Circuits Conference taking place here this week and each took a slightly different tack.

With Tulsa, a dual-core Xeon server chip from Intel coming in the second half of the year, the emphasis tips toward performance. The chip will run at 3.4GHz, faster than the 3GHz Xeon chip (formerly code-named Paxville) on the market today. Tulsa also comes with a 16MB unified cache, a large reservoir of memory on the chip for rapid data access. This means that each of the cores can access data from the entire cache. Presently, Intel and AMD dual-core chips sport segregated caches; dual-core chips from IBM come with a unified cache.

This change increases performance on some applications by up to 10 percent, said Nimish Modi, vice president of the Digital Enterprise Group at Intel. The chip will also be the first from Intel to incorporate Pellston, a virtualization technology that allows the chip to run multiple operating systems.

Tulsa will also contain energy conservation technology. The cache memory can go into sleep and deep sleep modes that can save up to 6 watts of energy consumption. In current chips, the cache remains on most of the time and inadvertently leaks electricity, which increases power consumption.

"The bulk of the power consumption in cache is through leakage," Modi said.

Still, Tulsa sports a thermal design power (or thermal ceiling) of 150 watts. That's lower than Paxville, which comes with a 165-watt TDP. Chips usually don't hit their thermal ceilings, but server manufacturers have to compensate for it in their designs. A high thermal ceiling can also translate to a high average power consumption.

By contrast, the Pacifica chip coming from AMD has a 95-watt thermal ceiling and will come with AMD's own virtualization technology, according to the company.

The two 512KB caches on Pacifica are also dedicated to the two cores. AMD won't have a unified cache until next year, according to the road map on the company's site.

See more CNET content tagged:
AMD Pacifica, ceiling, Intel Xeon, cache, power consumption


Join the conversation!
Add your comment
INTEL design is outdated
INTEL architecture is not scalable, that why INTEL needs 16MB of silicon to have reasonable performance. In contrast, all Opterons need is 1MB.

In some sense, those Xeons at 150 watts are overclocked chips, they can't really sustain the speced speed for long, it has to thermal throttle to prevent silicon meltdown.

<a class="jive-link-external" href="http://sharikou.blogspot.com" target="_newWindow">http://sharikou.blogspot.com</a>
Posted by sharikou (106 comments )
Reply Link Flag
Outdated because they haven't changed
The market has changed, and changed in a big way. Gone are the gigahertz races, which Intel is still playing a little. Now, it is multi-cores and energy conservation. Little wonder then you can't pick a flyer for Circuit City without seeing several PC with AMD chips now.
Posted by i_am_still_wade (250 comments )
Link Flag
An academic argument
Maybe a more efficient architecture wouldn't have needed that much cache. But still, Tulsa HAS the cache. :)
Posted by CompEng (201 comments )
Link Flag
But Intel already know this and are ditching the P4 as fast as they can. AMD on the other had have nothing special comming out for at least two years. With the 64 bit sillyness over now, all AMD have is HyperTransport. Aside from that there is very little separating the AMD64s from the Athlons.

(Incidentally, don't get me wrong and see me as a AMD hater. I am typing this on a Semperon 2600.)
Posted by Andrew J Glina (1673 comments )
Link Flag

Join the conversation

Add your comment

The posting of advertisements, profanity, or personal attacks is prohibited. Click here to review our Terms of Use.

What's Hot



RSS Feeds

Add headlines from CNET News to your homepage or feedreader.