Comments on: IBM chip architect guns for gigahertz
Unlike many colleagues, Power6 chief architect Brad McCredie continues to give clock speed priority in IBM's next-gen server processor.
Unlike many colleagues, Power6 chief architect Brad McCredie continues to give clock speed priority in IBM's next-gen server processor.
January 2, 2010 6:26 PM PST
January 2, 2010 4:56 PM PST
January 2, 2010 4:16 PM PST
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This being a part of their core (ie server) market, I think they will hit their marks.
era (385 vs 68020 vs 29000 vs SPARC), and my
basic conclusion is that only three things
matter:
-CPU Speed
-Bus Width
-Cache Size (or, more accuratley, the square root
of the cache size)
RISC vs CISC doesn't matter.
External bus speed matters, but not as much as
you'd think.
External bus mode (DDR or SDRAM) matters, but
mainly as a tie-breaker.
2-way versus 4-way versus 8-way cache doesn't
matter very much.
Two-level cache doesn't matter very much.
If IBM can build a 4 GHz processor with 4M
of reasonably good cache, then it will kick
the current generation of x86 processors out of
the server room. The big question is: What will
AMD and Intel come up with in the meantime?
Where will those PowerPC go ? embedded devices ?
- POWER and SPARC Comparisons made were...
- by DavidHalko July 2, 2006 6:53 PM PDT
- Interesting...
- Like this Reply to this comment
-
(8 Comments)> IBM has steadily gained share in the Unix server market against longtime leader Sun Microsystems in recent years...
Until the last quarter, when SUN had gained marketshare against all competitors.
> McCredie: The problem you find is this: When you go over and specialize too much on one aspect of performance, you generally get in trouble.
> McCredie: I don't believe there's a big role in this world for too-specialized hardware.
This was just the opposite message the IBM and POWER were delivering when Apple abandoned POWER ship.
IBM indicated that Apple was looking for a very high performance generic chip and they were more interested in investing in a more specialized infrastructure (around gaming machines.)
I find it ironic that the message is 100% the opposite direction now.
>>Power is a big issue these days. What will power consumption look like going from Power5 to Power6?
>McCredie: We're targeting the same classes and categories for Power5 and Power6. We're telling people we're hitting the same power envelope as with the Power5. We are holding the power aligned for the most part. Holding the power is a concern for everybody these days.
This is the same message that SUN had been evalgelizing with SPARC. They have gone through 3 generations of holding the power enveolope (uSPARC III, uSPARC IV, uSPARC IV+ - except their current processor is 3x the speed in a single thread and 5x the throughput considering multiple threads.
It has been an adventure watching POWER and SPARC go at it over the years:
- POWER coming out with 2 core per socket
- SPARC coming out with 8 core per socket
- POWER reaching out to 4 core per socket
This is the first time in awhile where SUN has been leading in nearly all market segments where vendors have needed to resort to MPP (very specialized software requirements) to beat a SUN manufactured single chassis platform (very easy to implement off-the-shelf software.)
I am looking forward to a reasonable response from proprietary POWER to put more pressure on Open Source architectures like SPARC.