Comments on: Intel shows test chips made on future processes

Moore's Law is on track, the chipmaker says, and it shows off 45-nanometer creations to prove it.
Photos: Intel's 45-nanometer process

Driving by Braille (Where IS That Wall?)

Room-temperature CMOS will hit the wall long
before 2020. I'd expect the 35 nanometer is
going to be real tough, and 25 nanometer looks
like it's made out of rocks. Here's the logic:

1. As you get smaller, tunneling current increases.
At 45 nm, tunneling current is about 50% of the
total power consumption. Tunneling current
increases exponentially as the dimensions shrink.

2. The easy way to reduce heating in general and
heating due to tunneling in particular is to
lower the operating voltage. Each generation
lately uses lower and lower voltage.

3. There are a lot of process issues with low
voltage operation, such as bandgap matching and
the need to reduce surface states below the
gate threshold voltage, but none of the process
issues are a showstopper. Thermal noise is the
problem.

4. At room temperature, thermal noise is about
0.033 volts (300 degrees Kelvin). If you scale
the voltage below about 0.333 volts, then you
are going to have thermal noise reliability
problems.

My conclusion is that the last room-temperature
chip technology will run at around 0.500 volts,
and will have a nominal feature size of 25 nm.
We can expect it to ship in 2010-2012, at
which time it's game over for the continuing
reduction in the size (and cost) of transistors.

The social and economic effects of the last doubling
will be very interesting to watch.

[Seaspray0]

Very informative

Mr. Chapman. You have a vast knowledge on this subject and I will look forward to reading your comments on the future. You may be right about it "hitting the wall" but as in the past I believe we will overcome them. It may take an intuitive leap such as going from tubes to solid state back in the 50's. There are alternatives to silicon on the periodic table that can be used for the substrate material. Perhaps one of these may provide a solution.

Driving by Braille (Where IS That Wall?)

Room-temperature CMOS will hit the wall long
before 2020. I'd expect the 35 nanometer is
going to be real tough, and 25 nanometer looks
like it's made out of rocks. Here's the logic:

1. As you get smaller, tunneling current increases.
At 45 nm, tunneling current is about 50% of the
total power consumption. Tunneling current
increases exponentially as the dimensions shrink.

2. The easy way to reduce heating in general and
heating due to tunneling in particular is to
lower the operating voltage. Each generation
lately uses lower and lower voltage.

3. There are a lot of process issues with low
voltage operation, such as bandgap matching and
the need to reduce surface states below the
gate threshold voltage, but none of the process
issues are a showstopper. Thermal noise is the
problem.

4. At room temperature, thermal noise is about
0.033 volts (300 degrees Kelvin). If you scale
the voltage below about 0.333 volts, then you
are going to have thermal noise reliability
problems.

My conclusion is that the last room-temperature
chip technology will run at around 0.500 volts,
and will have a nominal feature size of 25 nm.
We can expect it to ship in 2010-2012, at
which time it's game over for the continuing
reduction in the size (and cost) of transistors.

The social and economic effects of the last doubling
will be very interesting to watch.

[Seaspray0]

Very informative

Mr. Chapman. You have a vast knowledge on this subject and I will look forward to reading your comments on the future. You may be right about it "hitting the wall" but as in the past I believe we will overcome them. It may take an intuitive leap such as going from tubes to solid state back in the 50's. There are alternatives to silicon on the periodic table that can be used for the substrate material. Perhaps one of these may provide a solution.