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December 9, 2008 10:30 PM PST

Intel completes 32-nanometer chip development

by Brooke Crothers

Intel has completed the development phase of its next-generation manufacturing process that shrinks chip circuitry to 32 nanometers, the chipmaker said Tuesday night.

Intel 32-nanometer SRAM chip

Intel 32-nanometer SRAM chip

(Credit: Intel)

Intel processors are currently made on a 45nm process. Generally, smaller geometries result in faster and more power-efficient processors.

"The company is on track for production readiness of this future generation (of transistors)...in the fourth quarter of 2009," the chipmaker said in a statement.

Intel said it will provide technical details about the 32nm process technology at the International Electron Devices Meeting (IEDM) next week in San Francisco.

Finishing the development phase for 32nm process technology keeps Intel on track with its "tick-tock" strategy. Tick-tock is intended to introduce either a new processor microarchitecture or cutting-edge manufacturing process about every 12 months.

"Producing 32nm chips next year would mark the fourth consecutive year that Intel has met its goal," the company said.

The 32nm paper and presentation "describe a logic technology that incorporates second-generation high-k + metal gate technology, 193nm immersion lithography for critical patterning layers, and enhanced transistor strain techniques," Intel said.

Other Intel IEDM papers will "describe a low power system on chip version of Intel's 45nm process, transistors based on compound semiconductors, substrate engineering to improve performance of 45nm transistors, integrating chemical mechanical polish for the 45nm node and beyond; and, integrating an array of silicon photonics modulators," according to the company's statement.

Intel will also participate in a short course on 22nm CMOS technology.

Brooke Crothers is a former editor at large at CNET News.com, and has been an editor for the Asian weekly version of the Wall Street Journal. He writes for the CNET Blog Network, and is not a current employee of CNET. Contact him at mbcrothers@gmail.com. Disclosure.
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Add a Comment (Log in or register) (7 Comments)
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by Mr. Dee December 10, 2008 7:11 AM PST
Talk about well oiled machine. Although I don't understand a single thing you said in your last paragraph, it tells me one thing, AMD should be worried. I assume 22 NM by 2012, 10 NM by 2016 awesome to think about it.
Reply to this comment
by rapier1 December 10, 2008 8:02 AM PST
10nm seems unlikely. You can't keep shrinking component sizes indefinitely as they are already running into quantum effects. This doesn't mean we'll hit a processing wall - only that this aspect of the technology will have reached an effective limit.
by ducttape36 December 10, 2008 9:16 AM PST
never say never, especially in technology. quantum computing is making progress these days too.
by fokkwp December 10, 2008 8:24 AM PST
Ah, just in time for the next generations of Visa and OSX that will both feature 3 dimensional holographic images of the actual fonts in document thumbnails projected against real-time 64 frame per second live video feed wallpaper on 82" LCD monitors while we browse porn between sessions of downloading 12-gigabyte images of Aunt Martha from our Longs Drugstore disposable petrabyte digital cameras. We're not there yet, but when we are, Intel will lead the way!
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by mike_ekim December 10, 2008 10:30 AM PST
And when we get there, we'll still be waiting for the next improvement. =)
by EcuadorHomesOnline December 10, 2008 11:22 AM PST
This is incredible stuff. It seems not too long ago that the 1 micron barrier was broken, and now they're making transistors about one thirtieth of that size!
Reply to this comment
by Cyclonique December 16, 2008 1:37 AM PST
Actually with your numbers a linear strinkage from 1micron to 32nm actually is a reduction of almost 1000 in area size (not sure what the volumetric reduction would be but I assume not much in practice).
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About Nanotech - The Circuits Blog

Brooke Crothers was formerly editor-at-large at CNET News.com, an analyst at IDC (International Data Corp.) Japan, and an editor at The Asian Wall Street Journal Weekly (The Wall Street Journal, Dow Jones), among other endeavors, including a recent hiatus from the tech industry when he co-managed an after-school math and reading center. Nanotech covers computer chip technology and how it defines the computing experience. He is a member of the CNET Blog Network, and is not an employee of CNET. Disclosure.

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