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September 22, 2008 10:35 PM PDT

Tilera adds a 36-core chip

by Brooke Crothers
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Small start-up Tilera still beats chip giants like Intel handily on core counts. Tilera updated its line of many-core processors Monday, adding a 36-core version to the mix.

Tilera, which made a splash last year when it introduced its first 64-core processor, announced a scaled-down 36-core Tile processor on Monday, in order to broaden its market reach.

The TilePro36 "is giving us a midrange product. This type of device would be used in a high-end video conferencing (system)," said Bob Doud, who is the director of marketing at Tilera. The TilePro36 chip is also targeted at applications such as networking and security applications. "Anything in the one- to five-gigabit-per-second range," Doud said.

Along these lines, Doud also clarified the markets that Tilera is not targeting. "We target the embedded space. We don't target products like servers and home PCs," he said.

Tilera has also updated its original 64-core Tile64 to TilePro64 by doubling the performance while keeping the power consumption increase to less than 5 percent.

TilePro36 and TilePro64 processor key features

Key features of the TilePro36 and TilePro64 processors.

(Credit: Tilera)

The TilePro family improves the performance of highly threaded and shared-memory applications through the introduction of Dynamic Distributed Cache technology, according to Doud. "We've been able to double the performance of our caching system that supports threaded programming models," he said.

The TilePro processors have twice the level-1 cache memory of the previous generation and incorporate an additional on-chip communication network dedicated to cache management. Cache memory is crucial component for increasing processor performance.

In the Pro family, the "big breakthrough" is "making caching and cache coherence scalable as you start to go into more and more cores," according to Doud. In other words, designing the cache memory so it can be shared efficiently as more cores are added.

Tilera has also added new instruction set extensions for audio and video that deliver up to 2X improvement in multimedia signal processing.

So, what is the Tilera chip? The processors consist of small, individual building blocks, or tiles. Each tile has a RISC processing core that runs up to 866MHz as well as a switch that can send data in four directions: up, down, right, and left. These switches form a mesh network, called iMesh, that lets the chips communicate.

Each tile contains its own cache and the tiles can access all of the cache, depending on how it's programmed.

Power consumption is low for a many-core processor, using only between 10 and 16 watts for the 36-core version. Intel dual-core processors typically use over 25 watts.

The key to the chip's performance is tied to the nature of a distributed network. A network of slower processors can get jobs done quicker (in some cases) and with less overall energy than faster quad-core processors from Intel, for example, that have more complex cores.

The company say it now has more than 45 customers.

Brooke Crothers has served as an editor at large at CNET News, an editor at Dow Jones' Asian Wall Street Journal Weekly, and a senior editor at InfoWorld. His CNET blog covers chip technology and computer systems, and how they define the computing experience. He also contributes to The New York Times' Bits and Technology sections. He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure. Follow Brooke on Twitter @mbrookec.
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by man290663 September 25, 2008 8:29 AM PDT
This seems rather pointless!

Most OS's and applications are moving to 64 bit and this is only 16/32 bit compatible.. and even then the 32 bit rate is downgraded so much, it defeats the point of this. this looks like someone has tried the an old design and multiplied it ..

make it a true 64 bit device on a 64 parallel processing bus and then it will be newsworthy!
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Brooke Crothers has served as an editor at large at CNET News, an editor at Dow Jones' Asian Wall Street Journal Weekly, and a senior editor at InfoWorld. His CNET blog covers chip technology and computer systems, and how they define the computing experience. He also contributes to The New York Times' Bits and Technology sections. He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.

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