Live from Hot Chips 19: Session 9, Big Iron

Okay, this is it for Hot Chips. Read the whole set of Hot Chips blogs here. Comments? You know what to do...

This final session opens with a presentation by Sun of "Victoria Falls," a multicore server processor due out in 2008. This chip is the successor to the UltraSPARC T2, which was code-named "Niagara 2."

The cores on Victoria Falls (which I'll call VF for short) are basically the same as those on the T2. The big difference is that the new chip supports multi-chip configurations-- so customers of Sun's Throughput Computing systems can now go well beyond the 8 cores of the T2.

VF will run at the same speed as the T2-- currently 1.4 GHz. The T2 set records when it was introduced for the highest ever scores on the SPEC_rate multiprocessing benchmarks-- that is, for single-chip CPUs. At that, the scores were only slightly faster than those of IBM's Power6, which is just a dual-core chip. IBM's customers also have the option to use more than one Power6 in a single system, which isn't possible with the T2.

With VF, Sun customers will have the same option-- and if VF is faster than Power6 processors on a chip for chip basis, Sun will have a very compelling performance story next year. Power6 will still scale to larger systems, since VF is designed to support up to quad-chip configurations only (with external support chips)-- but larger servers than that tend to cost millions of dollars and sales volumes are low. Quad-processor servers are the sweet spot in the market.

Interestingly, VF lacks one of the major features of the T2: an on-chip 10-Gbit/s Ethernet controller. The extra complexity of multi-chip support may have pushed it out, and in a multi-chip system some of the Ethernet controllers probably would have gone to waste anyway.

Even more interestingly, around the middle of next year-- roughly when VF will be released-- Sun is planning to release the source code for the T2 under the GPL (version 2) open-source license. Some of the documentation is available now; the Verilog RTL code is being prepared for release next summer. For more information on this interesting program, visit the OpenSPARC website.

In this year's final Hot Chips presentation, IBM described the z6, the code name for its next mainframe processor. Do you remember the launch of the IBM System/360? If not, you're forgiven; the announcement was in April of 1964. How about the System/370 or System/390? Well, IBM's current "z Architecture" is the latest in that series. You think the x86 architecture is old? Are you impressed by Windows Vista's ability to run some old DOS programs? The zSeries machines support legacy binaries from 40 years ago.

The z6 is sort of a sibling of the Power6, which I covered yesterday (here). The z6 borrows major chunks of the Power6 design, although it runs a different instruction set. There are also many new design elements in the z6 to support the unique features of the z Architecture, such as the total of 894 instructions, including some for decimal math (to avoid problems with binary-to-decimal rounding, thus ensuring exact results for financial calculations).

The z6 is a quad-core design; I interpret this as an indicator that the z6 product line may start at a higher price point-- and with more cores-- than does the Power6 line. IBM is not yet talking about z6-based systems, but current zSeries servers get pretty big-- some, in fact, can weigh several tons. Big iron, indeed.

And now, if you'll excuse me, I'm going to go ice my hands...