On to the networking session at Hot Chips. Previous Hot Chips installments covered the Reed Hundt speech, AMD keynote, wireless networking, technology and software, process technology, multicore designs, IBM's Power6 efforts, Vernor Vinge's keynote address, and Nvidia. Other CNET coverage may be found here. Comments are welcome!
After the highly political talk by former FCC Chairman Reed Hundt, the Networking session pulled us sharply back into the engineering world.
The first presentation was from Bay Microsystems, describing the company's Chesapeake chip, a 50Gbps network processor with traffic management support.
I covered a lot of chips like this at Microprocessor Report. NPUs (network processors) tend to be highly optimized for networking, with custom interfaces, specially designed programmable cores, and other network-specific features.
Chesapeake is no exception. In fact, it reminds me strongly of the Xelerated X10q, a chip which won Microprocessor Report's Fifth Annual Analysts' Choice Award for "Best Extreme Processor."
Both chips share an unusual architecture--unlike conventional multicore processors where each core runs a sequence of instructions with associated data, the Xelerated and Bay designs move the packet data from one core to another, each core executing just one instruction. The data move, but the instructions don't. (See Figure 2 on this page at the Xelerated site for a visual idea of how this works.)
For algorithms that are relatively short and require little or no looping, this is a surprisingly efficient approach in spite of all the data movement. The key is that each time the data hop from one core to another, it's a very short hop. Also, this architecture is highly deterministic--the packet will definitely get all the processing it needs by the time it leaves the far end of the pipeline. It's also a simple programming model; to the programmer, there's apparently only one core.
In the Chesapeake design, the pipeline is over 300 stages long, which defines the limit on how much processing can be performed on each packet. Bay has optimized different segments of the pipeline to perform different functions, which adds slightly to the programming complexity--but it seems like a good tradeoff.
I doubt many CNET readers are designing 40Gbps network routers right now, but hey, if you are, you ought to check out the Chesapeake chip. And Xelerated's current X11, too.
Intel used to build a variety of application-specific products using StrongARM and XScale cores, since sold to Marvell. Tolapai is a break from this tradition and a return to Intel's strength in x86 processor design.
The x86 core on Tolapai was derived from the Pentium M mobile processor. Versions are available at clock speeds of 600MHz, 1066MHz and 1200MHz. The core is augmented by the QuickAssist unit to accelerate cryptography processing. Otherwise, it's a traditional SoC (system-on-chip) product--a big pile of peripherals and peripheral interfaces surrounding a processor core.
Tolapai is aimed at the embedded-processor market, for small single-board computer systems in networking, storage, and similar applications. It will compete with products from Cavium, Raza Microelectronics, and various other companies. Its unique selling proposition is its x86 compatibility--which isn't particularly important for this market, but some customers may find it useful.
Compared with Intel's PC and server business, all this embedded stuff is small beans, which tends to make potential customers nervous. How committed is Intel to these products? Well, who knows? Intel has shut down or sold off such product lines in the past.
The final talk in this session came from Fulcrum Microsystems, describing an Ethernet switch chip designed to support up to 24 ports of 10-gigabit Ethernet. That's the hot technology for high-end datacenters, and 24 switch ports on one chip is very impressive. But there isn't much to say about it that would be relevant here, so I'm going to give my wrists a rest for a few minutes and come back for Hot Chips session 8 on mobile PC processors.