November 2, 2009 5:45 AM PST

Tilera's balancing act: 100 cores vs. market realities

by Peter Glaskowsky
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While we're all familiar with the steady increase in the number of cores in mainstream PC and server processors, the corresponding progress in the embedded-processor market has been anything but steady.

With mainstream PC microprocessors standardizing on four-core designs such as Intel's Core i7 and leading-edge server chips ranging from 8 to 16 cores, single-core chips are no longer competitive. For embedded systems, however, one core may still be the right answer; if more are needed, the choices range up into the hundreds.

Tilera Tile-Gx100

The Tilera Tile-Gx100 combines 100 independent 64-bit integer processor cores and cryptographic accelerators with memory, network, and PCI Express interfaces.

(Credit: Tilera Corporation)

The latest announcement in the many-core embedded processor market is Tilera's Tile-Gx family, which combines 16 to 100 64-bit integer processor cores with cryptographic accelerators and off-chip interfaces for memory, networking, and PCI Express. I met with Tilera before last week's announcement to discuss the technical and business issues related to the Tile-Gx.

The technical details
San Jose, Calif.-based Tilera is eager to set itself apart from the many other chip companies competing in its target markets. Unlike most embedded processors with high core counts, for example, Tilera's design allows its cores to operate truly independently, even to the extent of running different operating systems if needed. More commonly, groups of tiles will be combined to run a single task that is part of a larger workload. In this way, one chip can operate like a cluster of multiprocessor systems.

Between this distinction and the fact that cores in the Tile-Gx family are a full 64 bits wide, Tilera claims the Tile-Gx100 is the "world's first 100-core processor." I think that's just a little too broad a claim, personally, since companies such as Clearspeed and Xelerated have previously made similar claims for their chips. Even more significantly, the Tile-Gx100 doesn't exist yet. It won't be a real product until early 2011, according to Tilera's current schedule.

Tile-Gx processors aren't something most CNET readers will ever knowingly use, though these chips will likely, eventually, help carry traffic over the public Internet and through larger corporate networks. But they do provide an excellent example of the issues facing PC processor vendors as core counts continue to grow.

Consider the Tile-Gx100 block diagram shown above. It's easy to imagine that this chip can get a lot of work done. Every core can run up to three instructions per cycle at up to 1.5GHz. It has dedicated hardware accelerators for cryptography and network packet processing. The network interfaces can implement up to eight 10Gb Ethernet ports. The chip also has four DDR3 memory interfaces; to reduce DRAM accesses, every core has 320KB of local cache memory. (The total amount of cache memory in the Tile-Gx100, about 32MB, matches that of IBM's Power7 processor, which has only eight cores.)

The need for balance
It's not so easy to keep all these resources busy, however. The more complicated a chip gets, generally speaking, the more difficult it becomes to make full use of its resources. This is what we often call the balance between hardware and software.

Tilera will offer four products in the Tile-Gx family with 16, 36, 64, and 100 cores and corresponding differences in memory and networking support. This range of products helps meet the needs of different applications, but each product still needs a particular balance of application requirements for maximum efficiency.

So here lies Tilera's great challenge--finding software applications that need a large amount of CPU performance and that also:

1. Are highly parallel, so they can keep many cores busy.
2. Don't need much (if any) floating-point math, since the Tile-Gx doesn't do that.
3. Can benefit from cryptographic acceleration.
4. Consume large amounts of network bandwidth.

Tilera wants customers to think of its chips as "general-purpose" processors, but as this list shows, they're better for some purposes than for others. As PC processors reach higher core counts and integrate more functionality, they too will become more sensitive to application requirements. Integration eventually reaches a point where additional complexity adds no practical value. And the closer PC processor vendors approach that limit, the more difficult it will become to sell their latest, greatest, most complicated chips.

Network processing is the most natural fit for Tilera's capabilities, particularly high-level services like virus scanning as I discussed in September (see "Insatiable demand for mobile data challenges industry"). Internet service providers rarely provide such services for PC users, since PCs can do their own scanning--but mobile phones and other Internet appliances often can't, so these services are seeing increasing demand.

The networking market, unfortunately, is not large enough to support a company like Tilera. Although there is a lot of networking equipment sold each year, each company in the business has its own ideas about how this processing should be done. A single chip design could never capture the majority of this potential demand.

Further, the larger equipment vendors often have policies in place against relying too heavily on individual suppliers, especially small start-ups. They will commonly design different products using different chip-level technology so that the failure of a single supplier--or the purchase of a supplier by a competing equipment vendor--will have only a limited effect on their bottom line.

New business opportunities
Tilera is working to develop new markets for its current TilePro and future Tile-Gx parts. The most significant of these new markets is cloud computing, which may favor solutions like Tilera's that offer higher performance per watt.

That's the metric Tilera touts most heavily for the Tile-Gx, promising 10 times the performance per watt of Intel's Westmere-EP, a six-core 32nm processor that Intel will begin shipping in 2010, which is aimed at high-efficiency servers. (Incidentally, I commend Tilera for making this comparison; Westmere-EP is exactly what they'll be competing against. Too often, chip companies will try to make themselves look better by comparing next year's products with last year's competition.)

Although 10x is a critical multiplier in this business (see my post "The factor factor"), such an advantage doesn't necessarily guarantee success. Tilera has done everything it can to minimize the difficulties associated with software development by adopting industry-standard development tools such as GCC and Eclipse, but its Tile chips still can't run Windows and it just can't match the developer relationships that companies like Advanced Micro Devices and Intel have established.

Fortunately, Tilera is small and relatively efficient for a chip company. Last month, Tilera announced that Quanta Computer invested $10 million in the company based on Quanta's interest in cloud computing. Tilera said it has enough funding to reach cash-flow breakeven in 2011, assuming the Tile-Gx reaches market and achieves the kind of success Tilera predicts.

I remain skeptical, but hopeful. I think there's no question that in the long run, there will be plenty of demand for complex, many-core processors like Tilera's. But will Tilera still be around by that time? And in the long run, once this demand develops, larger companies such as Intel will have their own offerings.

Can Tilera carve out a market niche that it can defend against such strong competition? I just don't know, but I'm always glad to see people trying new ideas.

Peter N. Glaskowsky is a computer architect in Silicon Valley and a technology analyst for the Envisioneering Group. He has designed chip- and board-level products in the defense and computer industries, managed design teams, and served as editor in chief of the industry newsletter "Microprocessor Report." He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.
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by tektaktyks November 2, 2009 6:34 AM PST
can it run osx and linux?
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by cloudmatt November 2, 2009 7:19 AM PST
more importantly will it play Crysis
by Peter N. Glaskowsky November 2, 2009 10:19 AM PST
Linux, yes. Darwin, probably, though I doubt anyone has done that port. OS X, no.

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by tektaktyks November 2, 2009 2:41 PM PST
i believe there is wine for darwin so that = crysis!:)
by krosafcheg November 2, 2009 7:59 AM PST
What instruction set does it execute?? How can you leave that info out of a story about a new processor!?
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by TrinityTrident November 2, 2009 9:20 AM PST
I agree. From what I can gather it's either MIPS or a MIPS based instruction set. In this day and age no one would be silly enough to launch an entirely new instruction set and all the engineering effort involved in a new compiler backend even if you use open source tools.
by Peter N. Glaskowsky November 2, 2009 10:24 AM PST
Well, this wasn't really a story about the details of the chip; for that, you can follow the link to the Tilera page on the Tile-Gx. But to save you the time, it's a proprietary VLIW instruction set. Presumably Tilera found it necessary to use a new instruction set for its Tile processors in order to reduce the size of the cores to the point where they could fit 64 to 100 of them on an affordable die.

It isn't really all that difficult to change the back end of gcc to support a simple new instruction set. I don't know how many person-months of work was required, but I'm sure that was a small part of Tilera's overall technical effort.

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by TrinityTrident November 2, 2009 11:08 AM PST
Peter,
I don't think it's a proprietary VLIW instruction, set but rather a MIPS derived VLIW instruction set. See this story -
http://www.theregister.co.uk/2009/10/26/tilera_third_gen_mesh_chips/print.html
"Three years ago, Tilera had licensed SGI's MIPS-based C/C++ compilers for the Tile chips"

Even if the compiler backend work isn't much, it takes a fair bit of work to get all the userland binaries and the associated OSes working for an *entirely new* instruction set. Sure it can and has been done, but I doubt that Tilera has the level of resources from what you are mentioning. I'm also very surprised that they are trying to hide this information from you. It won't take very long to find this out if someone had access to Tilera's binaries or their GCC port. Since GCC is GNU GPL where exactly have they contributed their code changes back? It should be easy enough to find out given that. I'm willing to bet its MIPS based. You of course have the option of just asking them point blank. Lets see if they do tell you.
by Peter N. Glaskowsky November 2, 2009 11:08 PM PST
Perhaps someone from Tilera will comment, but to my way of thinking, the phrase "MIPS-derived VLIW instruction set" is logically equivalent to "proprietary VLIW instruction set". :-)

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by TroyBailey November 3, 2009 10:32 AM PST
Tilera's instruction set is similar to MIPS. It is Tilera's ISA. Tilera has a complete set of development tools including a C/C++ compiler, debugger, profiler, IDE, etc. Our customers tell us it is the best multicore toolset they have used.

Compiling applications written in C/C++ such as open source applications is very straight forward. Of course the tools also facilitate creating new applications; our hypervisor software layer handles much of the "housekeeping".

We have ported Standard SMP Linux. Neither Windows, nor OSX have been ported to our chips. Tilera's processors are not targeted at desktop use at this time.

Troy Bailey
VP Marketing, Tilera Corporation
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by cp256 November 3, 2009 10:59 AM PST
How about internet server use? Complex spam filtering and virus checking email can suck the life out of a server. I'd love to test something like that with that many cores.
by Peter N. Glaskowsky November 3, 2009 5:55 PM PST
Thanks, Troy.

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by epobirs November 6, 2009 12:51 AM PST
Remember what WINE stands for as an acronym: WINE is Not an Emulator. Yes, it is a nest acronym.

WINE provides substitutes for the Windows API that map to the appropriate functions in the host OS. It assumes x86 compatible hardware running the whole show. Unless Crysis is written in purely portable code, which is highly doubtful, you going to need x86 emulation in addition to WINE. It could be done but would likely lose nearly all of the value of using the Tilera hardware.

It seems to me that Tilera faces more challenge from Nvidia, AMD/ATI, and perhaps some mutant offspring of Larrabee.
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by scwuffy November 10, 2009 4:33 AM PST
It resembles a really fat FPGA does it not?
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About Speeds and Feeds

Silicon Valley-based computer architect and chip analyst Peter N. Glaskowsky attends a variety of industry conferences throughout the year to meet with industry thought leaders and dig into the future of computing technology. In Speeds and Feeds, he analyzes trends in system architecture and interface design, as well as market and political pressures surrounding those trends. He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.

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